Network-off-Chip (M)
From iis-projects
Contents
Overview
Status: Completed
- Type: Semester Thesis or Master Thesis
- Professor: Prof. Dr. L. Benini
- Supervisors:
Introduction
As the demand for High-Performance Computing (HPC) systems continues to increase, traditional on-chip communication networks, such as bus-based and point-to-point interconnects, are becoming inefficient and limiting the scalability of these systems. Network-on-Chip (NoC) architectures have emerged as a promising solution to this problem, providing a scalable and flexible communication infrastructure for HPC systems. However, off-chip communication remains a bottleneck for many NoC architectures. This thesis proposes a Network-off-chip architecture that combines a NoC with an off-chip serial link to overcome the limitations of traditional NoC architectures.
Project
In this project, you will combine the FlooNoC[1][2] with the Serial Link[3] to end up with an interconnect that can bridge both on-chip and off-chip communication. This will require rethinking and redesigning our existing IPs for the FlooNoC and the Serial Link.
Protocol conversion
First, the protocol interface of the Serial Link and the FlooNoC is not compatible yet. The Serial Link has an AXI4-Interface [4], while the FlooNoC has a generic protocol that wraps AXI4 requests and responses. Theoretically, unwrapping the generic NoC protocol to AXI with a NI would solve the problem but cause an overhead that is not desirable. Instead, a module that converts from the generic NoC protocol to AXI-Stream should replace the current protocol layer module.
Physical vs. Virtual Channels
The design FlooNoC is based on wide physical channels since on-chip routing resources are plentiful. Wire pitches for on-chip routing are in the order of nm, compared to μBump pitches which are tens of μm. Hence, going off-chip requires some form of serialization. Serializer/Deserializer (SERDES) is very common in traditional NoCs, in the form of wide messages that are serialized to multiple narrow messages. Further, virtual channels also serialize multiple channels onto one physical channel to save wires. While physical channels are replacing virtual channels in modern technologies, virtual channels are still needed to go off-chip. One part of this thesis will be to define and implement a bridge from multiple wide physical channels to narrow virtual channels that can be sent off-chip while achieving low latency and high throughput and energy efficiency.
Narrow-Wide communication
Communication in modern SoCs can be quite diverse regarding the interconnect requirements. Direct Memory Accesss (DMAs) for instance, require an interconnect that can satisfy a high sustained bandwidth. They are also more latency-tolerant if they can issue multiple outstanding transactions (see AXI-protocol), data can be transferred in bursts and double-buffered such that PEs can be kept busy during data transfers. on the other hand messages issued by PEs are usually more latency-sensitive (e.g., synchronization). This is why FlooNoC implements multiple physical channels with different widths for wide, high-bandwidth and narrow latency-sensitive traffic. The physical2virtual channel bridge must also arbitrate between narrow and wide while preventing starvation and deadlocks and guaranteeing sustained high-bandwidth and low-latency transfers.
Character
- 20% Literature Research
- 50% Architecture Design and Exploration
- 20% Performance evaluation
- 10% Documentation & Report
Prerequisites
- Experience with digital design in SystemVerilog as taught in VLSI I
- Knowledge about non-coherent on-chip protocols (e.g. AXI4) is recommended
