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Network-on-Chip for coherent and non-coherent traffic (M)

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Overview

Status: Available

Introduction

With the continuous growth in the number of cores in many-core architectures, effective communication between the cores has become very important. Network on Chip (NoC) designs, functioning as an interconnection backbone, are pivotal in ensuring efficient communication. While we have already done a lot of work on a NoCs called 'FlooNoC' [1][2] for non-coherent traffic using the AXI protocol [3][4], we are now also looking into supporting coherent traffic, particularly in shared memory systems.

As established by ARM, the Coherent Hub Interface (CHI) standard [5] provides a protocol for such coherent interconnects. Combining coherent traffic (as per the CHI standard) with non-coherent traffic in a single NoC system presents a valuable yet challenging endeavor. This thesis aims to investigate and develop an integrated NoC design to accommodate both traffic types.

Project

The goals of this thesis are as follows:

1. To understand the specific requirements and characteristics of coherent traffic as defined by the CHI standard.

2. To analyze the existing NoC designs for non-coherent traffic using the AXI protocol and identify the primary bottlenecks when introducing coherent traffic.

3. To develop an architectural design for an integrated NoC that can seamlessly support both coherent and non-coherent traffic.

4. To implement a prototype of the proposed design and benchmark its performance in various scenarios.

Character

  • 20% Literature Research
  • 50% Architecture Design and Exploration
  • 20% Performance
  • 10% Documentation & Report

Prerequisites

  • Experience with digital design in SystemVerilog as taught in VLSI I
  • Knowledge about Coherency Protocol (e.g. MESI) is recommended
  • Knowledge about non-coherent on-chip protocols (e.g. AXI4) is recommended

References

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