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<!-- Integration of Alibaba’s T-Head Opene906 processor in PULP -->
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[[Category:Digital]]
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= Introduction =
 
= Introduction =
  
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Alibaba has recently (October 2021) introduced a range of RISC-V processors with the Xuantie family ranging from the E902 micro-controller class core to the C910 core for servers in data centers. This also includes the XuanTie C906 core found in the Allwinner D1 single-core RISC-V processor.
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Today’s real-time systems require fast interrupt handling to manage asynchronous requests coming from the surrounding environment. This means that the underlying HW should guarantee a fast propagation of the interrupt line towards the core, with a per-interrupt, fine-grained control over each line, and support interrupt preemption and nesting according to each event priority.
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T-Head had open-sourced four RISC-V-based Xuantie series processor cores, namely Xuantie E902, E906, C906, and C910, as well as related software and tools [1].
 
  
 
= Project =
 
= Project =
  
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PULPissimo is an open-source, single core RISC-V microcontroller [5] developed by PULP that hosts an industrial-grade processor, namely CV32E40P [4].  
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PULPissimo is an open-source, single core RISC-V microcontroller [4] developed by PULP that hosts an industrial-grade processor, namely CV32E40P [3].
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RISC-V Core Local Interrupt Controller (CLIC) [2] is a standardized interrupt controller for RISC-V core subsuming the original RISC-V local interrupt scheme (CLINT). It promises pre-emptive, low-latency, vectored, priority/level based interrupts.
  
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The goal of this project is to replace our in-house processor with T-Head’s Opene906:
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The goal of this project is to replace the current interrupt handler in PULPissimo with the CLIC.
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* Study T-Head’s opene906 source code.
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* For the latter, at IIS we have forked T-Head’s processors in our environment (Mentor Questa for RTL simulation and SW toolchain building) [3] to ease development/usage bring-up overhead.
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In particular:
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* Integrate T-Head’s opene906 into PULPissimo to replace the existing processor developed by PULP, CV32E40P
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* Study CLIC reference specifications [2] and PULP’s CLIC implementation [1]
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* Integrate PULP’s CLIC into PULPissimo to replace the existing interrupt controller
 
* Verify basic functional correctness in simulation
 
* Verify basic functional correctness in simulation
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* Synthesize the new processor, evaluate area and timing figures
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* Investigate HW/SW extensions based on known CLIC implementations, such as [5] and [6]
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* Synthesize the design, giving particular attention to the CLIC overhead with respect to the original baseline
 
* ASIC Backend flow towards PULPissimo SoC tapeout
 
* ASIC Backend flow towards PULPissimo SoC tapeout
  
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= References =
 
= References =
  
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[1] https://github.com/T-head-Semi (GitHub repository)
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[1] https://github.com/pulp-platform/clic
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[2] https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc
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[3] https://github.com/bluewww/opene906 (GitHub repository)
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[3] https://github.com/openhwgroup/cv32e40p
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[4] https://github.com/pulp-platform/pulpissimo
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[4] https://github.com/openhwgroup/cv32e40p (GitHub repository)
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[5] https://github.com/bluewww/opene906
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[6] https://doc.nucleisys.com/nuclei_spec/isa/eclic.html
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[5] https://github.com/pulp-platform/pulpissimo (GitHub repository)
 

Revision as of 16:12, 31 January 2022


Overview

Status: Available

Introduction

Today’s real-time systems require fast interrupt handling to manage asynchronous requests coming from the surrounding environment. This means that the underlying HW should guarantee a fast propagation of the interrupt line towards the core, with a per-interrupt, fine-grained control over each line, and support interrupt preemption and nesting according to each event priority.

Project

PULPissimo is an open-source, single core RISC-V microcontroller [4] developed by PULP that hosts an industrial-grade processor, namely CV32E40P [3]. RISC-V Core Local Interrupt Controller (CLIC) [2] is a standardized interrupt controller for RISC-V core subsuming the original RISC-V local interrupt scheme (CLINT). It promises pre-emptive, low-latency, vectored, priority/level based interrupts.

The goal of this project is to replace the current interrupt handler in PULPissimo with the CLIC.

In particular:

  • Study CLIC reference specifications [2] and PULP’s CLIC implementation [1]
  • Integrate PULP’s CLIC into PULPissimo to replace the existing interrupt controller
  • Verify basic functional correctness in simulation
  • Investigate HW/SW extensions based on known CLIC implementations, such as [5] and [6]
  • Synthesize the design, giving particular attention to the CLIC overhead with respect to the original baseline
  • ASIC Backend flow towards PULPissimo SoC tapeout

Character

  • 15% Literature / architecture review
  • 30% RTL implementation
  • 30% Backend
  • 25% Evaluation

Prerequisites

  • Experience with digital design in SystemVerilog as taught in VLSI I
  • Must have visited VLSI II in a previous semester or take it alongside the thesis

References

[1] https://github.com/pulp-platform/clic [2] https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc [3] https://github.com/openhwgroup/cv32e40p [4] https://github.com/pulp-platform/pulpissimo [5] https://github.com/bluewww/opene906 [6] https://doc.nucleisys.com/nuclei_spec/isa/eclic.html

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