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PULP’s CLIC extensions for fast interrupt handling

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Status: Available


Alibaba has recently (October 2021) introduced a range of RISC-V processors with the Xuantie family ranging from the E902 micro-controller class core to the C910 core for servers in data centers. This also includes the XuanTie C906 core found in the Allwinner D1 single-core RISC-V processor. T-Head had open-sourced four RISC-V-based Xuantie series processor cores, namely Xuantie E902, E906, C906, and C910, as well as related software and tools [1]. Xuantie E902 and E906 processors implement the Core-Local Interrupt Controller (CLIC) [2], a newly proposed RISC-V interrupt controller promising low-latency, vectored, pre-emptive interrupts to meet the needs of Real-Time embedded systems.


At IIS we recently developed an in-house CLIC IP, which is coupled with the CV32E40P processor [4] within the PULPissimo SoC platform. PULPissimo is a RISC-V microcontroller [5] developed by PULP.

The goal of this project is to:

  • Study the RISC-V CLIC specifications and T-Head’s CLIC source code.
  • For the latter, at IIS we have forked T-Head’s processors in our environment (Mentor Questa for RTL simulation and SW toolchain building) [3] to ease development/usage bring-up overhead.
  • Integrate T-Head’s CLIC into PULPissimo and couple it with CV32E40P
  • Verify functional correctness in simulation and measure interrupt latency
  • Synthesize and compare with PULP’s CLIC (area/timing reports)
  • ASIC Backend flow towards PULPissimo SoC tapeout


  • 10% Literature / architecture review
  • 40% RTL implementation
  • 30% Backend
  • 20% Evaluation


  • Experience with digital design in SystemVerilog as taught in VLSI I
  • Must have visited VLSI II in a previous semester or take it alongside the thesis


[1] (GitHub repository)

[2] (GitHub repository)

[3] (GitHub repository)

[4] (GitHub repository)

[5] (GitHub repository)