Personal tools

Difference between revisions of "PULPonFPGA: Lightweight Virtual Memory Support - Coherency Extensions"

From iis-projects

Jump to: navigation, search
Line 13: Line 13:
 
: ... Set up operation on the evaluation platform, and characterize the enhanced solution using heterogeneous benchmark applications.
 
: ... Set up operation on the evaluation platform, and characterize the enhanced solution using heterogeneous benchmark applications.
  
===Status: In progress ===
+
===Status: Completed ===
 
: Conrad Burchert
 
: Conrad Burchert
 
<!--: Looking for Interested Master Students --->
 
<!--: Looking for Interested Master Students --->
Line 47: Line 47:
 
[[#top|↑ top]]
 
[[#top|↑ top]]
 
[[Category:Digital]]
 
[[Category:Digital]]
[[Category:In progress]]
+
[[Category:Completed]]
 
[[Category:Semester Thesis]]
 
[[Category:Semester Thesis]]
 
[[Category:PULP]]
 
[[Category:PULP]]
Line 56: Line 56:
 
[[Category:Marongiu]]
 
[[Category:Marongiu]]
 
[[Category:PSocrates]]
 
[[Category:PSocrates]]
 +
[[Category:2016]]
  
 
<!--  
 
<!--  

Revision as of 15:17, 11 April 2016

Pulp on fpga.png

Short Description

While high-end heterogeneous systems-on-chip (SoCs) are increasingly supporting heterogeneous uniform memory access (hUMA) as envisioned by the Heterogeneous System Architecture (HSA) foundation, their low-power counterparts targeting the embedded domain still lack basic features like virtual memory support for accelerators. As opposed to simply passing virtual address pointers, explicit data management involving copies is needed to share data between host processor and accelerators which hampers programmability and performance.

At IIS, we use an evaluation platform based on the Xilinx Zynq-7000 SoC with PULPonFPGA implemented in the programmable logic to study the integration of programmable many-core accelerators into embedded heterogeneous SoCs. We have developed a mixed hardware/software solution to enable lightweight virtual memory support for many-core accelerators in heterogeneous embedded SoCs. Based on a content-addressable memory (CAM), efficiently managed by a kernel-level driver module running on the host, our solution features a considerably lower design complexity compared to conventional input/output memory management units (IOMMUs).

The idea of this project is to enhance our solution to support the accelerator coherency port (ACP) of the Zynq SoC, which allows the accelerator to access the low-latency on-chip memories of the host including L1 and L2 data caches and scratchpad memories.

This system design project requires work to be done at several layers of abstraction. More precisely, you will need to:

... Extend the hardware of the remapping address block (RAB) to support the ACP of the Zynq SoC.
... Extend the Linux kernel-level driver managing the RAB
... Extend the user-space runtime of the host to control the driver
... Set up operation on the evaluation platform, and characterize the enhanced solution using heterogeneous benchmark applications.

Status: Completed

Conrad Burchert
Supervision: Pirmin Vogel, Michael Schaffner, Andrea Marongiu

Character

10% Theory, Algorithms and Simulation
30% VHDL, FPGA Design
50% Linux Kernel-Level Driver Development
10% User-space Runtime and Application Development for Host and Accelerator

Prerequisites

VLSI I,
VHDL/System Verilog, C
Embedded Linux experience
Experience with Linux kernel-level driver development is of advantage.

Professor

Luca Benini

Publications

  • P. Vogel, A. Marongiu, L. Benini, "Lightweight Virtual Memory Support for Many-Core Accelerators in Heterogeneous Embedded SoCs", Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'15), Amsterdam, The Netherlands, 2015

Links

  • Xilinx Zynq-7000 All-Programmable SoC [1]
  • PULP [2]

↑ top