Routing 1000s of wires in Network-on-Chips (1-2S/M)
From iis-projects
Contents
Overview
Status: Available
- Type: Semester Thesis or Master Thesis
- Professor: Prof. Dr. L. Benini
- Supervisors:
Introduction
The bandwidth requirements in modern HPC systems pose a serious challenge for the design of the next generation of Network-on-Chips (NoCs). On the other hand, modern technologies have provided us with a lot of possibilities on how to approach the implementation of NoCs. For instance, modern technologies have >10 metal layers, which provide a lot of routing resources (>50k wires/mm) to route the links of a NoC. Another example is the placement of SRAM macros, which usually consume a lot of the area, but if handled smartly, the wires of a Network-on-Chip can be routed over the SRAM macros.
In our research group we implemented our own Network-on-Chip called FlooNoC [1][2], which was designed with awareness of those physical implementation effects and hence uses very wide and multiple separate physical channels. While we have done some initial backend explorations, there are a lot of open questions that can be explored in this thesis.
Project
This thesis aims to go deeper into the backend design and optimization of Network-on-Chips. The specific areas of exploration can include:
Router Symbiosis: Should the routers be hardened as a macro or flattened into the top-level/tile? There are a lot of reasons that speak for and against each option. For instance, flattening the routers is easier for the backend designer, but you lose control over how the routing is done by the EDA tools, and it is possibly not optimal.
Routing channel length and density: How long can the wires maximally be, such that the timing is still met? And how close can wires be routed to each other without sacrificing signal integrity?
Gas Stations: If the wires are too long, the paths are usually buffered with so-called gas stations to bridge the larger distances. This can be done either by the designer manually or by the EDA tool automatically. What is the best strategy to do this? i.e., how many buffers should be placed for a certain distance and which driving strengths are needed for the best timing and power consumption?
Performance and Energy: How can we maximize the frequency of the NoC while keeping the power consumption in check? Is it better to increase the width of the channels or to increase the frequency of the links?
Character
- 10% Literature Research
- 60% Architecture Design and Exploration
- 20% Simulation and Evaluation
- 10% Documentation & Report
Prerequisites
- The student should have attended the VLSI 2 course.
- Previous backend experience (i.e. a chip tapeout) is advantageous but not required
- Some familiarity with the concept of Network-on-Chips is recommended
