Scan Chain Fault Injection in a PULP SoC (1S)
From iis-projects
Overview
Status: Available
- Type: Semester Thesis
- Professor: Prof. Dr. L. Benini
- Supervisors:
Introduction
At IIS, we recently taped out two ASICs with features for fault tolerance, increasing redundancy to radiation-induced errors, e.g. for Space applications.
Both of these Chips (Cerberus and Trikarenos) have been tested, but additional functionality to inject faults using scan chains has not been fully evaluated.
Project
In this project, you will extend the initial trial fault injection setup to verify and test a chip with injected faults. To understand what is going on in the chip, you will corroborate these experiments with RTL simulations, understand the limitations of the design, and develop improved architectural support for scan chain fault injection testing.
Character
- 50% Chip Testing & Software setup
- 30% RTL Design
- 20% Documentation & Evaluation
Prerequisites
- Familiarity with ASIC design and testing as taught in VLSI4
