User contributions
From iis-projects
- 14:25, 2 May 2024 (diff | hist) . . (-4) . . Accelerating Matrix Multiplication on a 216-core MPSoC (1M) (current)
- 14:25, 2 May 2024 (diff | hist) . . (-2) . . A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S) (current)
- 14:24, 2 May 2024 (diff | hist) . . (-2) . . A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S) (→Status: In progress)
- 18:58, 21 April 2024 (diff | hist) . . (-12) . . A RISC-V ISA Extension for Scalar Chaining in Snitch (M) (→Project description) (current)
- 18:57, 21 April 2024 (diff | hist) . . (-25) . . A RISC-V ISA Extension for Scalar Chaining in Snitch (M) (→Introduction)
- 11:49, 13 March 2024 (diff | hist) . . (-22) . . GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S) (current)
- 11:49, 13 March 2024 (diff | hist) . . (+76) . . GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S) (→Status: In progress)
- 11:47, 13 March 2024 (diff | hist) . . (+2) . . A RISC-V ISA Extension for Scalar Chaining in Snitch (M)
- 11:45, 13 March 2024 (diff | hist) . . (-4) . . A reduction-capable AXI XBAR for fast M-to-1 communication (1M) (current)
- 11:44, 13 March 2024 (diff | hist) . . (+15) . . A RISC-V ISA Extension for Scalar Chaining in Snitch (M) (→Status: Available)
- 12:53, 7 March 2024 (diff | hist) . . (+7) . . A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S) (→References)
- 12:52, 7 March 2024 (diff | hist) . . (+197) . . A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S)
- 14:05, 5 March 2024 (diff | hist) . . (-109) . . GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S) (→Status: Available)
- 17:40, 1 March 2024 (diff | hist) . . (+91) . . A RISC-V ISA Extension for Scalar Chaining in Snitch (M) (→Status: Available)
- 21:33, 22 February 2024 (diff | hist) . . (-18) . . User:Colluca (→Luca Colagrande) (current)
- 21:30, 22 February 2024 (diff | hist) . . (+14) . . A RISC-V ISA Extension for Scalar Chaining in Snitch (M) (→Detailed task description)
- 21:28, 22 February 2024 (diff | hist) . . (+7,539) . . N A RISC-V ISA Extension for Scalar Chaining in Snitch (M) (Created page with "<!-- A RISC-V ISA Extension for Scalar Chaining in Snitch (1M) --> Category:Digital Category:High Performance SoCs Category:2024 Category:Master Thesis Cate...")
- 19:52, 22 February 2024 (diff | hist) . . (0) . . Efficient collective communications in FlooNoC (1M) (current)
- 19:51, 22 February 2024 (diff | hist) . . (+4) . . Efficient collective communications in FlooNoC (1M)
- 16:54, 21 February 2024 (diff | hist) . . (+81) . . Efficient collective communications in FlooNoC (1M) (→Status: Available)
- 16:35, 16 February 2024 (diff | hist) . . (-1) . . User:Colluca (→Luca Colagrande)
- 16:34, 16 February 2024 (diff | hist) . . (+34) . . User:Colluca (→Luca Colagrande)
- 12:43, 3 November 2023 (diff | hist) . . (0) . . User:Colluca (→Luca Colagrande)
- 12:42, 3 November 2023 (diff | hist) . . (+7) . . User:Colluca (→Luca Colagrande)
- 12:42, 3 November 2023 (diff | hist) . . (+51) . . User:Colluca (→Luca Colagrande)
- 12:28, 3 November 2023 (diff | hist) . . (0) . . Efficient collective communications in FlooNoC (1M) (→Introduction)
- 12:28, 3 November 2023 (diff | hist) . . (+6) . . Efficient collective communications in FlooNoC (1M) (→Introduction)
- 12:21, 3 November 2023 (diff | hist) . . (0) . . Efficient collective communications in FlooNoC (1M) (→Introduction)
- 12:20, 3 November 2023 (diff | hist) . . (+108) . . N File:Floonoc paper fig4.png (Physical implementation of FlooNoC connecting a mesh of compute tiles in GlobalFoundries’ 12 nm technology) (current)
- 12:18, 3 November 2023 (diff | hist) . . (+59) . . Efficient collective communications in FlooNoC (1M) (→Introduction)
- 12:17, 3 November 2023 (diff | hist) . . (-74) . . Efficient collective communications in FlooNoC (1M) (→Project description)
- 12:13, 3 November 2023 (diff | hist) . . (+12) . . Efficient collective communications in FlooNoC (1M) (→Project description)
- 12:12, 3 November 2023 (diff | hist) . . (+5,693) . . N Efficient collective communications in FlooNoC (1M) (Created page with "<!-- Efficient collective communications in FlooNoC (1M) --> Category:Digital Category:High Performance SoCs Category:2023 Category:Master Thesis Category:H...")
- 11:21, 20 October 2023 (diff | hist) . . (+180) . . A reduction-capable AXI XBAR for fast M-to-1 communication (1M)
- 15:51, 17 October 2023 (diff | hist) . . (+138) . . Accelerating Matrix Multiplication on a 216-core MPSoC (1M)
- 09:57, 17 October 2023 (diff | hist) . . (+107) . . A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S) (→Stretch goals)
- 09:57, 17 October 2023 (diff | hist) . . (+73) . . A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S) (→Detailed task description)
- 09:56, 17 October 2023 (diff | hist) . . (-67) . . A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S) (→Stretch goals)
- 11:37, 16 October 2023 (diff | hist) . . (+131) . . Accelerating Matrix Multiplication on a 216-core MPSoC (1M)
- 15:12, 3 October 2023 (diff | hist) . . (-19) . . Accelerating Matrix Multiplication on a 216-core MPSoC (1M) (→References)
- 15:12, 3 October 2023 (diff | hist) . . (0) . . Accelerating Matrix Multiplication on a 216-core MPSoC (1M) (→References)
- 15:11, 3 October 2023 (diff | hist) . . (+7) . . Accelerating Matrix Multiplication on a 216-core MPSoC (1M) (→References)
- 15:11, 3 October 2023 (diff | hist) . . (+21) . . Accelerating Matrix Multiplication on a 216-core MPSoC (1M) (→References)
- 15:10, 3 October 2023 (diff | hist) . . (+272) . . Accelerating Matrix Multiplication on a 216-core MPSoC (1M) (→References)
- 18:22, 29 September 2023 (diff | hist) . . (+2) . . A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S)
- 18:21, 29 September 2023 (diff | hist) . . (+2) . . A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S) (→Status: Available)
- 18:21, 29 September 2023 (diff | hist) . . (+79) . . A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S)
- 18:19, 29 September 2023 (diff | hist) . . (+2) . . Accelerating Matrix Multiplication on a 216-core MPSoC (1M)
- 18:19, 29 September 2023 (diff | hist) . . (+83) . . Accelerating Matrix Multiplication on a 216-core MPSoC (1M)
- 18:17, 29 September 2023 (diff | hist) . . (-2) . . Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
- 18:16, 29 September 2023 (diff | hist) . . (+3) . . A reduction-capable AXI XBAR for fast M-to-1 communication (1M) (→Status: Reserved)
- 13:46, 5 September 2023 (diff | hist) . . (+91) . . A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S) (→Status: Available)
- 11:20, 5 September 2023 (diff | hist) . . (+4) . . A reduction-capable AXI XBAR for fast M-to-1 communication (1M) (→Detailed task description)
- 11:20, 5 September 2023 (diff | hist) . . (+62) . . A reduction-capable AXI XBAR for fast M-to-1 communication (1M) (→Detailed task description)
- 17:18, 4 September 2023 (diff | hist) . . (-19) . . Accelerating Matrix Multiplication on a 216-core MPSoC (1M) (→References)
- 17:18, 4 September 2023 (diff | hist) . . (+5,919) . . N Accelerating Matrix Multiplication on a 216-core MPSoC (1M) (Created page with "<!-- Accelerating Matrix Multiplication on a 216-core MPSoC (1M) --> Category:Digital Category:High Performance SoCs Category:2023 Category:Master Thesis Ca...")
- 16:24, 4 September 2023 (diff | hist) . . (+1) . . Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S) (→Status: Available)
- 16:24, 4 September 2023 (diff | hist) . . (+11) . . Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
- 00:03, 10 August 2023 (diff | hist) . . (+6,677) . . N A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S) (Created page with "<!-- A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S) --> Category:Digital Category:High Performance SoCs Category:2023 Category:Maste...")
- 00:03, 10 August 2023 (diff | hist) . . (+51) . . N File:Snitch block diagram.png (A block diagram of the Snitch cluster architecture.) (current)
- 15:53, 9 August 2023 (diff | hist) . . (+1) . . High Performance SoCs (→Matteo Perotti)
- 15:53, 9 August 2023 (diff | hist) . . (0) . . High Performance SoCs (→Luca Colagrande)
- 15:52, 9 August 2023 (diff | hist) . . (0) . . Matteo Perotti (→Contact Information) (current)
- 15:52, 9 August 2023 (diff | hist) . . (0) . . User:Colluca (→Contact)
- 15:19, 12 May 2023 (diff | hist) . . (+12) . . A reduction-capable AXI XBAR for fast M-to-1 communication (1M) (→Detailed task description)
- 15:18, 12 May 2023 (diff | hist) . . (+53) . . A reduction-capable AXI XBAR for fast M-to-1 communication (1M) (→Detailed task description)
- 15:10, 12 May 2023 (diff | hist) . . (+2) . . A reduction-capable AXI XBAR for fast M-to-1 communication (1M)
- 15:09, 12 May 2023 (diff | hist) . . (-2) . . A reduction-capable AXI XBAR for fast M-to-1 communication (1M) (→Status: Available)
- 15:09, 12 May 2023 (diff | hist) . . (+7) . . A reduction-capable AXI XBAR for fast M-to-1 communication (1M) (→References)
- 15:07, 12 May 2023 (diff | hist) . . (+32) . . A reduction-capable AXI XBAR for fast M-to-1 communication (1M) (→Stretch goals)
- 15:06, 12 May 2023 (diff | hist) . . (0) . . A reduction-capable AXI XBAR for fast M-to-1 communication (1M) (→Stretch goals)
- 15:06, 12 May 2023 (diff | hist) . . (-13) . . A reduction-capable AXI XBAR for fast M-to-1 communication (1M) (→Stretch goals)
- 15:05, 12 May 2023 (diff | hist) . . (+36) . . A reduction-capable AXI XBAR for fast M-to-1 communication (1M) (→Detailed task description)
- 15:03, 12 May 2023 (diff | hist) . . (+1) . . A reduction-capable AXI XBAR for fast M-to-1 communication (1M)
- 15:01, 12 May 2023 (diff | hist) . . (0) . . N File:Occamy block diagram.png (current)
- 15:01, 12 May 2023 (diff | hist) . . (+98) . . A reduction-capable AXI XBAR for fast M-to-1 communication (1M)
- 14:53, 12 May 2023 (diff | hist) . . (-1,663) . . A reduction-capable AXI XBAR for fast M-to-1 communication (1M)
- 14:53, 12 May 2023 (diff | hist) . . (-84) . . A reduction-capable AXI XBAR for fast M-to-1 communication (1M) (→Project description)
- 14:39, 12 May 2023 (diff | hist) . . (+1,536) . . A reduction-capable AXI XBAR for fast M-to-1 communication (1M)
- 11:03, 12 May 2023 (diff | hist) . . (+1,667) . . A reduction-capable AXI XBAR for fast M-to-1 communication (1M)
- 10:15, 12 May 2023 (diff | hist) . . (+34) . . N File:Axi xbar.png (A block diagram of our AXI XBAR IP) (current)
- 10:14, 12 May 2023 (diff | hist) . . (+6,257) . . N A reduction-capable AXI XBAR for fast M-to-1 communication (1M) (Created page with "<!-- A reduction-capable AXI XBAR for fast M-to-1 communication (1M) --> Category:Digital Category:High Performance SoCs Category:2023 Category:Master Thesis...")
- 14:56, 11 May 2023 (diff | hist) . . (+101) . . Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
- 13:19, 20 January 2023 (diff | hist) . . (+99) . . Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
- 22:29, 19 January 2023 (diff | hist) . . (0) . . Accelerating Stencil Workloads on Snitch using ISSRs (1-2S/B) (current)
- 22:28, 19 January 2023 (diff | hist) . . (0) . . Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
- 22:28, 19 January 2023 (diff | hist) . . (0) . . GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S)
- 13:03, 13 January 2023 (diff | hist) . . (+95) . . Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S) (→Status: Available)
- 15:14, 22 November 2022 (diff | hist) . . (0) . . Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
- 15:12, 22 November 2022 (diff | hist) . . (+1,058) . . Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
- 12:25, 27 October 2022 (diff | hist) . . (+3) . . High Performance SoCs (→Who are we)
- 12:24, 27 October 2022 (diff | hist) . . (+218) . . High Performance SoCs
- 12:09, 26 October 2022 (diff | hist) . . (+4) . . Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S) (→Optional stretch goals)
- 12:08, 26 October 2022 (diff | hist) . . (+13) . . Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S) (→Detailed task description)
- 14:13, 13 October 2022 (diff | hist) . . (0) . . GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S)
- 14:13, 13 October 2022 (diff | hist) . . (0) . . N File:Gdb logo.png (current)
- 14:12, 13 October 2022 (diff | hist) . . (+52) . . GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S)
- 14:08, 13 October 2022 (diff | hist) . . (-20) . . User:Colluca (→Available Projects)
- 14:08, 13 October 2022 (diff | hist) . . (-20) . . User:Colluca (→Completed Projects)
- 14:07, 13 October 2022 (diff | hist) . . (-20) . . User:Colluca (→Projects In Progress)
- 13:40, 13 October 2022 (diff | hist) . . (+36) . . GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S)
- 13:33, 13 October 2022 (diff | hist) . . (+5) . . GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S) (→Your learnings)
- 13:32, 13 October 2022 (diff | hist) . . (+6) . . User:Colluca
- 11:39, 13 October 2022 (diff | hist) . . (+56) . . GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S) (→Project description)
- 11:38, 13 October 2022 (diff | hist) . . (-10) . . GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S) (→Project description)
- 11:38, 13 October 2022 (diff | hist) . . (+18) . . GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S) (→Project description)
- 11:36, 13 October 2022 (diff | hist) . . (+76) . . GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S)
- 11:36, 13 October 2022 (diff | hist) . . (+192) . . GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S) (→Project description)
- 11:33, 13 October 2022 (diff | hist) . . (-2) . . GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S) (→Prerequisites)
- 11:32, 13 October 2022 (diff | hist) . . (+2) . . GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S) (→Prerequisites)
- 11:32, 13 October 2022 (diff | hist) . . (+92) . . GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S) (→Prerequisites)
- 11:30, 13 October 2022 (diff | hist) . . (+151) . . GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S) (→Your learnings)
- 11:23, 13 October 2022 (diff | hist) . . (+3) . . GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S) (→Optional stretch goals)
- 11:23, 13 October 2022 (diff | hist) . . (+6) . . GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S) (→Your learnings)
- 11:22, 13 October 2022 (diff | hist) . . (+58) . . GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S) (→Your learnings)
- 11:19, 13 October 2022 (diff | hist) . . (+912) . . GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S) (→Project description)
- 10:56, 13 October 2022 (diff | hist) . . (+54) . . GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S) (→Project description)
- 10:53, 13 October 2022 (diff | hist) . . (-18) . . GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S) (→Introduction)
- 10:51, 13 October 2022 (diff | hist) . . (-9) . . GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S) (→Introduction)
- 10:51, 13 October 2022 (diff | hist) . . (-7) . . GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S) (→Introduction)
- 10:51, 13 October 2022 (diff | hist) . . (+7) . . GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S) (→Introduction)
- 10:50, 13 October 2022 (diff | hist) . . (0) . . GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S) (→Introduction)
- 10:49, 13 October 2022 (diff | hist) . . (+1) . . GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S) (→Introduction)
- 01:02, 13 October 2022 (diff | hist) . . (-86) . . A Post-Simulation Trace-Based RISC-V GDB Debugging Server (Blanked the page) (current)
- 01:01, 13 October 2022 (diff | hist) . . (0) . . m GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S) (Colluca moved page A Post-Simulation Trace-Based RISC-V GDB Debugging Server to GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S))
- 01:01, 13 October 2022 (diff | hist) . . (+86) . . N A Post-Simulation Trace-Based RISC-V GDB Debugging Server (Colluca moved page A Post-Simulation Trace-Based RISC-V GDB Debugging Server to GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S))
- 01:01, 13 October 2022 (diff | hist) . . (+1) . . GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S) (→Project description)
- 00:59, 13 October 2022 (diff | hist) . . (+205) . . GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S)
- 00:53, 13 October 2022 (diff | hist) . . (-189) . . GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S)
- 23:47, 12 October 2022 (diff | hist) . . (+335) . . GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S)
- 23:20, 12 October 2022 (diff | hist) . . (+5,783) . . N GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S) (Created page with "<!-- A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S) --> Category:Digital Category:High Performance SoCs Category:2022 Category:Semester Thesis...")
- 14:48, 12 October 2022 (diff | hist) . . (+13) . . Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
- 11:48, 12 October 2022 (diff | hist) . . (-86) . . Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)) (Blanked the page) (current)
- 11:48, 12 October 2022 (diff | hist) . . (0) . . m Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S) (Colluca moved page Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)) to Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S))
- 11:48, 12 October 2022 (diff | hist) . . (+86) . . N Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)) (Colluca moved page Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)) to Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S))
- 11:46, 12 October 2022 (diff | hist) . . (-87) . . Benchmarking a heterogeneous 217-core MPSoC on HPC applications (Blanked the page) (current)
- 11:46, 12 October 2022 (diff | hist) . . (0) . . m Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S) (Colluca moved page Benchmarking a heterogeneous 217-core MPSoC on HPC applications to Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)))
- 11:46, 12 October 2022 (diff | hist) . . (+87) . . N Benchmarking a heterogeneous 217-core MPSoC on HPC applications (Colluca moved page Benchmarking a heterogeneous 217-core MPSoC on HPC applications to Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)))
- 11:42, 12 October 2022 (diff | hist) . . (-45) . . Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
- 11:35, 12 October 2022 (diff | hist) . . (-18) . . User:Colluca
- 11:33, 12 October 2022 (diff | hist) . . (-9) . . Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S) (→References)
- 11:33, 12 October 2022 (diff | hist) . . (+16) . . Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S) (→References)
- 11:33, 12 October 2022 (diff | hist) . . (+50) . . Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S) (→References)
- 11:32, 12 October 2022 (diff | hist) . . (+55) . . Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S) (→Optional stretch goals)
- 11:24, 12 October 2022 (diff | hist) . . (+31) . . Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
- 11:23, 12 October 2022 (diff | hist) . . (+38) . . Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
- 11:16, 12 October 2022 (diff | hist) . . (+11) . . Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
- 11:15, 12 October 2022 (diff | hist) . . (+29) . . Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
- 11:14, 12 October 2022 (diff | hist) . . (+53) . . Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S) (→Prerequisites)
- 11:13, 12 October 2022 (diff | hist) . . (-19) . . Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S) (→Prerequisites)
- 11:12, 12 October 2022 (diff | hist) . . (+18) . . Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S) (→Detailed task description)
- 01:32, 12 October 2022 (diff | hist) . . (-5) . . Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
- 01:32, 12 October 2022 (diff | hist) . . (0) . . Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
- 01:28, 12 October 2022 (diff | hist) . . (+4) . . User:Colluca (→Luca Colagrande)
- 01:25, 12 October 2022 (diff | hist) . . (-7) . . Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S) (→Detailed task description)
- 01:24, 12 October 2022 (diff | hist) . . (+12) . . Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S) (→Project)
- 01:22, 12 October 2022 (diff | hist) . . (+9) . . Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S) (→Stretch goals)
- 01:21, 12 October 2022 (diff | hist) . . (-8) . . Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S) (→Project)
- 01:21, 12 October 2022 (diff | hist) . . (+174) . . Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S) (→Project)
- 01:19, 12 October 2022 (diff | hist) . . (-167) . . Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S) (→Stretch goals)
- 01:19, 12 October 2022 (diff | hist) . . (+23) . . Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S) (→Stretch goals)
- 01:18, 12 October 2022 (diff | hist) . . (+6) . . Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S) (→Detailed task description)
- 01:17, 12 October 2022 (diff | hist) . . (+23) . . Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S) (→Detailed task description)
- 01:16, 12 October 2022 (diff | hist) . . (+54) . . Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S) (→Project)
- 01:14, 12 October 2022 (diff | hist) . . (+535) . . Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
- 00:06, 12 October 2022 (diff | hist) . . (+28) . . Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
- 00:05, 12 October 2022 (diff | hist) . . (+1,011) . . Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
- 20:51, 11 October 2022 (diff | hist) . . (0) . . Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
- 18:19, 11 October 2022 (diff | hist) . . (+35) . . Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
- 18:15, 11 October 2022 (diff | hist) . . (-77) . . Test project (Blanked the page) (current)
- 18:14, 11 October 2022 (diff | hist) . . (0) . . m Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S) (Colluca moved page Test project to Benchmarking a heterogeneous 217-core MPSoC on HPC applications)
- 18:14, 11 October 2022 (diff | hist) . . (+77) . . N Test project (Colluca moved page Test project to Benchmarking a heterogeneous 217-core MPSoC on HPC applications)
- 18:13, 11 October 2022 (diff | hist) . . (-1) . . Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
- 18:12, 11 October 2022 (diff | hist) . . (+26) . . N Category:Colluca (Redirected page to User:Colluca) (current)
- 18:10, 11 October 2022 (diff | hist) . . (+3,710) . . N Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S) (Created page with "<!-- Benchmarking a heterogeneous 217-core MPSoC on HPC applications (1S) --> Category:Digital Category:High Performance SoCs Category:Acceleration_and_Transprecisi...")
- 17:00, 11 October 2022 (diff | hist) . . (+18) . . User:Colluca
- 14:25, 16 August 2022 (diff | hist) . . (+1,284) . . N User:Colluca (Created page with "=Luca Colagrande= thumb | 200px| I received my B.Sc. from Politecnico di Milano in Electronics Engineering and my M.Sc. in Electrical Engineer...")
- 14:02, 16 August 2022 (diff | hist) . . (0) . . N File:Colluca picture.png (current)
- 13:59, 16 August 2022 (diff | hist) . . (+24) . . Accelerating Stencil Workloads on Snitch using ISSRs (1-2S/B)
- 13:57, 16 August 2022 (diff | hist) . . (+71) . . Accelerating Stencil Workloads on Snitch using ISSRs (1-2S/B)
- 13:53, 16 August 2022 (diff | hist) . . (+28) . . N File:Stencils.png (Some example stencil filters) (current)