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• Interfacing PULP with a Brain-Inspired Ultra-Low Power Spiking Cochlea
  1. design a low-power interface in standard cell technology that could be used to lin ...the cochleaLP sensor. In this target, the interface resides on a low-power FPGA (e.g. an a MicroSemi IGLOO).
  9 KB (1,427 words) - 18:36, 5 September 2019
• LightProbe
  ...hardware (phone, tablet, workstation) for post-processing over a standard digital link as simple as a standard peripheral, like a camera. * Implementation of processing subunits: Hardware design FPGA/ASIC (VHDL/HLS)
  2 KB (254 words) - 14:14, 31 October 2020
• Single-Bit-Synapse Spiking Neural System-on-Chip
  ...IBM TrueNorth architecture [Merolla14], a homogeneous fabric of 1 million digital spiking neurons that can be used for visual classification at a very low po ...omize and use this neuron to create a scalable spiking neuron for FPGA and ASIC targets. Whereas that work marked a starting point for the development of a
  7 KB (1,000 words) - 12:22, 13 January 2017
• Convolution Neural Networks on our Ultra-Low Power Mult-Core Plattform PULP
  [[Category:Software]] [[Category:FPGA]] [[Category:ASIC]] [[Category:Semester Thesis]] [[Category:Master Thesis]] [[Category:2016] Around the middle of the project there is a design review, where senior members of the lab review your work (bring all the rel
  6 KB (823 words) - 08:36, 20 January 2021
• Energy-Efficient Brain-Inspired Hyperdimensional Computing
  : 40% Architecture Design * '''[[Design Review]]'''
  4 KB (467 words) - 13:38, 10 November 2020
• Autoencoder Accelerator for On-Chip Semi-Supervised Learning
  [[Category:Digital]] [[Category:FPGA]] [[Category:ASIC]] [[Category:Semester Thesis]] [[Category:Master Thesis]] [[Category:2016]] ...ccess which can be exploited by an application-specific integrated circuit ASIC, in contrast to CPUs or even GPUs.
  6 KB (842 words) - 08:37, 20 January 2021
• Hardware Accelerators for Lossless Quantized Deep Neural Networks
  ...ly quantized CNNs (''YodaNN'' [Andri2017]), in the Ergo project we want to design a PULP-based entire computation cluster around a set of deep, fast and low- ...er the QNE should be an extension to the currently existing XNE or a novel design based on the same building blocks.
  6 KB (949 words) - 13:41, 10 November 2020
• Embedded Audio Source Localization Exploiting Coincidence Detection in Asynchronous Spike Streams
  * AER-SPI interface, implemented on an ULP FPGA development board (see [http://iis-projects.ee.ethz.ch/index.php/Interfacin AER-SPI interface is a custom IP hosted on an ULP FPGA development board. It efficiently collects and stores the data produced asy
  7 KB (1,025 words) - 19:52, 30 May 2017
• A computational memory unit using phase-change memory devices
  ...t. The ideal candidate should be well versed in digital and analog circuit design with hands on experimental experience. A strong mathematical background and : Basics of Digital and Analog Design (VLSI1/AIC)
  4 KB (546 words) - 11:33, 17 April 2020
• Deep Learning for Brain-Computer Interface
  [[Category:Digital]] [[Category:FPGA]]
  3 KB (372 words) - 20:22, 1 April 2019
• Resilient Brain-Inspired Hyperdimensional Computing Architectures
  In this project, your goal would be to design and develop an end-to-end robust HD processor with extremely resilient cont : 40% Architecture Design
  3 KB (401 words) - 19:08, 29 January 2021
• Trace Debugger for custom RISC-V Core
  # Specification, RTL design and host software development of a trace debugger for one of our custom RIS # FPGA evaluation of your implementation.
  5 KB (729 words) - 11:27, 11 December 2018
• Efficient Search Design for Hyperdimensional Computing
  ...arch operations in HD computing. You would develop RTL implementation with FPGA prototyping. : Architecture Design
  3 KB (366 words) - 15:39, 10 November 2020
• Creating a HDMI Video Interface for PULP
  ...ted native differential signalling this is easier to implement in a purely digital fashion. ...ip (or external) frame-buffer. At first your implementation will target an FPGA (Xilinz Zynq) implementation as a first prototype but upon successful compl
  4 KB (603 words) - 09:37, 10 July 2018
• BigPULP: Multicluster Synchronization Extensions
  ...combines a modern ARMv8 multicluster CPU with a Xilinx Virtex-7 XC7V2000T FPGA [7] capable of implementing PULP [1] with 4 to 8 clusters and a total of 32 : 50% Implementation (VHDL, FPGA/ASIC Design, C)
  6 KB (805 words) - 12:17, 22 January 2018
• BigPULP: Shared Virtual Memory Multicluster Extensions
  ...combines a modern ARMv8 multicluster CPU with a Xilinx Virtex-7 XC7V2000T FPGA [7] capable of implementing PULP [1] with 4 to 8 clusters and a total of 32 : 50% Implementation (C, VHDL, FPGA/ASIC Design)
  6 KB (801 words) - 15:05, 23 August 2018
• Hyper Meccano: Acceleration of Hyperdimensional Computing
  * '''[[Design Review]]''' [[Category:Digital]]
  3 KB (409 words) - 13:58, 9 November 2017
• IoT Turbo Decoder
  [[File:High Throughput Turbo Decoder Design.png|400px|thumb|A previous, high throughput, Turbo Decoder developed at IIS ...processor cluster. The final design can either be mapped to an FPGA, or an ASIC.
  3 KB (427 words) - 09:37, 14 September 2018
• High Speed FPGA Trigger Logic for Particle Physics Experiments
  ...phys.ethz.ch/ Physics Department of ETH Zurich]. If you are experienced in FPGA programming (VHDL) and want to spice up your knowledge with a real world, t ...puts that connect to the AC701’s FMC connector and get familiar with the design of the unit and it’s purpose.
  4 KB (460 words) - 21:42, 30 January 2018
• Wireless Communication Systems for the IoT
  ...ns, which incorporate analog sensor / actuator front ends, RF-transceiver, digital baseband processing, and an application processor. Such a RF System-on-Chip ...an RF SoC design is the hardware- and energy-efficient realization of the digital baseband algorithms in which we constantly offer various semester and maste
  3 KB (344 words) - 01:45, 10 February 2021

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