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• Baseband Processor Development for 4G IoT
  The goal of this project is to design a processor using existing components and port it to an FPGA-based prototyping platform
  2 KB (347 words) - 17:58, 14 April 2016
• An FPGA-Based Testbed for 4G/LTE Mobile Communication
  #REDIRECT [[Baseband Processor Development for 4G IoT]]
  55 bytes (7 words) - 14:46, 28 May 2015
• Improving our Smart Camera System
  ...X1 board to get best performance transferring data from the sensor to the processor. ..., E. Culurciello and Y. LeCun, "NeuFlow: A Runtime Reconfigurable Dataflow Processor for Vision", Proc. IEEE ECV'11@CVPR'11 [http://ieeexplore.ieee.org/xpls/icp
  8 KB (1,176 words) - 16:26, 30 October 2020
• System Analysis and VLSI Design of NB-IoT Baseband Processing
  [[File:lteTestbed.jpg|thumb|Figure 2: LTE testbed with digital baseband and processor on an FPGA and RF-IC on the [[evaLTE]] FMC module.]]
  2 KB (245 words) - 10:39, 6 November 2017
• Implementing Hibernation on the ARM Cortex M0
  ...ailable before the power outage, i.e., the supply voltage is dropping, the processor state can be saved only when a power outage is imminent and thus superfluou Both scenarios require a mechanism to save a snapshot of the processor state in a non-volatile memory. This mechanism is commonly known as '''hibe
  3 KB (390 words) - 11:59, 20 June 2016
• Design of State Retentive Flip-Flops
  ...ation to be retained between two calls, it is not acceptable for an entire processor core idling, for example while waiting for a DMA transfer to be completed.
  2 KB (364 words) - 09:34, 25 July 2017
• Standard Cell Compatible Memory Array Design
  ...ocks of any processing system, in fact most of the performance of a modern processor is determined by its ability to efficiently store and retrieve data. For IC
  5 KB (769 words) - 15:54, 23 May 2018
• Intelligent Power Management Unit (iPMU)
  ...PMU should schedule the system tasks in an optimal way and wakeup the main processor if required. Naturally, the iPMU should consume as little power as possible
  2 KB (292 words) - 11:40, 2 June 2021
• Change-based Evaluation of Convolutional Neural Networks
  ..., E. Culurciello and Y. LeCun, "NeuFlow: A Runtime Reconfigurable Dataflow Processor for Vision", Proc. IEEE ECV'11@CVPR'11 [http://ieeexplore.ieee.org/xpls/icp
  5 KB (747 words) - 18:04, 29 August 2016
• Rethinking our Convolutional Network Accelerator Architecture
  ..., E. Culurciello and Y. LeCun, "NeuFlow: A Runtime Reconfigurable Dataflow Processor for Vision", Proc. IEEE ECV'11@CVPR'11 [http://ieeexplore.ieee.org/xpls/icp
  9 KB (1,263 words) - 18:52, 12 December 2016
• Design of a VLIW processor architecture based on RISC-V
  ...of this project are rather challenging as the VLSI architecture of a VLIW processor is by far more complex than that of a RISC architecture. We therefore recom ...Thesis]] [[Category:2016]] [[Category:ASIC]] [[Category:PULP]] [[Category:Processor]]
  3 KB (377 words) - 10:25, 5 November 2019
• Minimal Cost RISC-V core
  ...n are the most important requirements of such a system. For this purpose a processor which only supports the basic instructions is enough. A very simple 2-3stag ...Thesis]] [[Category:2016]] [[Category:ASIC]] [[Category:PULP]] [[Category:Processor]]
  3 KB (384 words) - 17:24, 21 August 2019
• Turbo Equalization for Cellular IoT
  [[Category:Processor]]
  3 KB (450 words) - 11:43, 13 November 2018
• PULPonFPGA: Hardware L2 Cache
  ...icit data management involving copies is needed to share data between host processor and accelerators which hampers programmability and performance.
  5 KB (711 words) - 10:27, 5 November 2019
• NextGenChannelDec
  [[Category:Processor]]
  3 KB (402 words) - 15:31, 13 April 2016
• Next Generation Channel Decoder
  [[Category:Processor]]
  3 KB (418 words) - 14:01, 13 November 2020
• Implementation of a NB-IoT Positioning System
  ...ftware co-design in which part of the algorithm will be mapped onto a PULP processor while computational complex tasks are realized in dedicated hardware accele [[Category:Processor]]
  4 KB (555 words) - 16:36, 23 May 2018
• Design of a Fused Multiply Add Floating Point Unit
  ...ated in the pipeline. In a multi-processor environment one private FPU per processor core is not the most energy efficient implementation because ''floating poi ...multiply-add FPU, implement it in System Verilog and plug it to the RISC-V processor.
  2 KB (346 words) - 10:26, 5 November 2019
• PULPonFPGA: Lightweight Virtual Memory Support - Page Table Walker
  ...icit data management involving copies is needed to share data between host processor and accelerators which hampers programmability and performance.
  5 KB (712 words) - 17:57, 7 November 2017
• PULPonFPGA: Lightweight Virtual Memory Support - Physically Contiguous Memory
  ...icit data management involving copies is needed to share data between host processor and accelerators which hampers programmability and performance.
  6 KB (866 words) - 13:43, 29 November 2019

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