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• Ultra-low power processor design
  ...hitecture. We will use a state of the art 28nm SOI process to evaluate the performance of the processor. ====Energy Efficient Computing using Multicore Systems====
  10 KB (1,669 words) - 19:01, 30 January 2014
• Exploitation of Inherent Error Resilience of Wireless Systems under Unreliable Silicon
  ...P TD-HSPA wireless communication system (receive side). Bottom: Throughput performance of the system including re-transmissions with hybrid-ARQ for various defect ...the future requires a paradigm shift from the assumption of 100% reliable computing to fault-tolerant
  2 KB (343 words) - 13:56, 9 February 2015
• Digital
  rect 0 0 1300 910 [[High Performance SoCs]] * '''[[High Performance SoCs]]'''
  7 KB (811 words) - 15:21, 23 February 2024
• Acceleration and Transprecision
  ...ccelerators are not limited to high performance sector alone. In low power computing, they allow complex tasks such as computer vision or cryptography to be per
  2 KB (275 words) - 17:05, 24 November 2023
• Ultra-Efficient Visual Classification on Movidius Myriad2
  ...f 12 SHAVE processors, that leverage VLIW and SIMD operations to achieve a high level of energy efficiency. The SHAVE processors share a 2MB tightly couple # Measurement of performance and energy efficiency of the proposed solution
  4 KB (593 words) - 14:57, 30 November 2016
• Covariant Feature Detector on Parallel Ultra Low Power Architecture
  The development of a CV library featuring high level capabilities is key tackling real word problems such as wearable devi ...to operate on a large range of operating voltages, achieving in this way a high level of energy efficiency over a wide range of application workloads.
  4 KB (628 words) - 16:16, 20 February 2018
• FPGA acceleration of ultrasound computed tomography for in vivo tumor screening
  ...s able to perform accurate tomographic reconstruction of SoS/AA, providing high-contrast tumor images. In the next months, this technology will be evaluate ...creening procedure in medical trials, we now aim at incorporating portable computing platforms as an add-on to conventional ultrasound systems. This platforms w
  3 KB (411 words) - 14:07, 30 August 2017
• A Wireless Sensor Network for HPC monitoring
  ...ed by wireless links. We want to apply this scenario to a High Performance Computing (HPC) infrastructure for environmental monitoring, aiming at an improving o ...cation (simulations), measuring power-consumption, and assessing detection performance in lab. conditions
  5 KB (617 words) - 16:22, 27 February 2018
• Signal-Processing and Data-Compression on Beaglebone Black used as embedded HPC-performance-monitoring device
  ...ng architectures are facing power/thermal challenges that are limiting the performance benefits of technology scaling. However, even if energy-efficiency is of pr ...en-source ARM-Linux loss-less implementations when available) for the best performance on our application-scenario.
  3 KB (351 words) - 16:19, 27 February 2018
• Linux Driver for built-in ADC using DMA and Programmable Real-Time Unit (PRU) support on Beaglebone Black used as embedded HPC-performance-monitoring device
  ...ng architectures are facing power/thermal challenges that are limiting the performance benefits of technology scaling. However, even if energy-efficiency is of pr
  3 KB (394 words) - 16:19, 27 February 2018
• Control an external ADC using Programmable Real-Time Unit (PRU) Subsystem on Beaglebone Black used as embedded HPC-performance-monitoring device
  ...ng architectures are facing power/thermal challenges that are limiting the performance benefits of technology scaling. However, even if energy-efficiency is of pr ...d at the node power-supply. Such routing-board will integrate a high-speed high-resolution ADC, which will be controlled by the built-in Programmable Real-
  3 KB (440 words) - 16:15, 1 September 2017
• Open Power-On Chip Controller Study and Integration
  ...re a set of interested partners shares HW and SW IPs to create competitive computing node systems. The power8 CPUs features an interesting power management design where the computing cores are coupled with a dedicated PPC 405 hard real-time core, which imple
  3 KB (462 words) - 15:57, 9 September 2016
• Linux Driver for fine-grain and low overhead access to on-chip performance counters
  ...ng architectures are facing power/thermal challenges that are limiting the performance benefits of technology scaling. Optimizing for energy efficiency requires m ...ce with external monitors and not with the internal per-core architectural performance counters.
  3 KB (417 words) - 15:55, 9 September 2016
• Interfacing PULP with a Brain-Inspired Ultra-Low Power Spiking Cochlea
  ...at the same time can benefit from the availability of a level of computing performance orders of magnitude better than that of ultra-low power microcontrollers. * [Cassidy13] A. S. Cassidy et al., “Cognitive computing building block: A versatile and efficient digital neuron model for neurosyn
  9 KB (1,427 words) - 18:36, 5 September 2019
• Deep Learning Projects
  ...rties make DNNs an ideal fit for modern SIMD architectures and distributed computing systems. ...each data sample. Hence, to reduce the pressure of DNNs on the underlying computing infrastructure, research in computational deep learning has focussed on two
  18 KB (2,473 words) - 19:29, 19 February 2024
• BigPULP: Multicluster Synchronization Extensions
  ...figurations in multiple technology nodes [1]. A key component allowing for high energy-efficiency is the Event Unit Flex, i.e., a highly versatile, program ...e and features widely-tunable performance, e.g., to use use PULP as a high-performance parallel accelerator in heterogeneous systems. To this end, we also study t
  6 KB (805 words) - 12:17, 22 January 2018
• BigPULP: Shared Virtual Memory Multicluster Extensions
  ...figurations in multiple technology nodes [1]. A key component allowing for high energy-efficiency is the Event Unit Flex, i.e., a highly versatile, program ...e and features widely-tunable performance, e.g., to use use PULP as a high-performance parallel accelerator in heterogeneous systems. To this end, we also study t
  6 KB (801 words) - 15:05, 23 August 2018
• Neural Networks Framwork for Embedded Plattforms
  ...ly trained reduced-precision networks reach similar performance than their high-precision equivalents. In previous projects, we have successfully developed ...-based special-purpose instructions on the PULP platform to accelerate the computing task.
  3 KB (317 words) - 14:40, 14 April 2021
• HERO: TLB Invalidation
  ...e and features widely-tunable performance, e.g., to use use PULP as a high-performance parallel accelerator in heterogeneous systems. To this end, we also study t ...ous Embedded SoCs", ''ESWEEK special issue of ACM Transactions on Embedded Computing Systems'' [https://dl.acm.org/citation.cfm?id=3126560 link]
  6 KB (796 words) - 17:19, 18 November 2019
• Heterogeneous SoCs
  ...terogeneous integration has allowed (not only) Apple to get high computing performance under tight power constraints.]] ...Heterogeneous systems on chip''' are currently one of the main drivers for performance-per-energy advancements in various application domains.
  3 KB (421 words) - 18:41, 28 October 2020
• Energy Efficient Autonomous UAVs
  ...al class of devices used for such sophisticated algorithms are multi-cores high-end CPUs and embedded heterogeneous systems featuring powerful CPUs coupled Nowadays is well known how UAVs with high-level autonomous navigation capabilities are a hot topic both in industry a
  14 KB (2,077 words) - 15:02, 13 June 2022
• Real-Time Implementation of Quantum State Identification using an FPGA
  ...e only at the end of 20th century, but it requires the development of high performance electronic devices. The research on the development of these electronic dev ...in significant experience with signal processing in the context of quantum computing experiments and FPGA hardware implementations
  5 KB (599 words) - 09:03, 21 December 2017
• Design of a 25 Gbps SerDes for optical chip-to-chip communication
  ...d memory has doubled only every 30 months, becoming the bottleneck of high performance computers. ...n the optical domain can bypass those issues, allowing power efficient and high transmission rates.
  3 KB (382 words) - 11:44, 20 August 2021
• Ternary Weights Engine For Efficient Many Channels Spike Sorting Applications
  ..., the data streams that reflect the underlying neuron activity can present high spatial correlation among neighboring channels. This poses new challenges r * Evaluate Power/Performance/Area of the proposed implementation.
  5 KB (741 words) - 10:05, 18 November 2019
• Wireless Sensing With Long Range Comminication (LoRa)
  ...ce since low power microprocessors are weak in terms of computation power. High computation microprocessor are power hungry though. For these reasons, mult ...cation (simulations), measuring power-consumption, and assessing detection performance in lab. conditions
  5 KB (744 words) - 15:37, 10 November 2020
• AMZ Driverless Competition Embedded Systems Projects
  ...competition we started our second season willing to improve robustness and performance even further. We hope to be faster than a human driver in the coming years. ...cameras and an IMU allowing running visual inertial algorithms in the main computing system. In addition, some image processing should be done at this system to
  6 KB (895 words) - 16:27, 30 October 2020
• IBM Research
  ...n architecture, huge amounts of data need to be shuttled back and forth at high speeds, a task at which this architecture is inefficient. ...omputing paradigms from in-memory computing to brain-inspired neuromorphic computing. Our research spans from devices and architectures to algorithms and applic
  9 KB (1,330 words) - 15:20, 15 March 2024
• Finite Element Simulations of Transistors for Quantum Computing
  computing. The existing C++ code at IIS that solves this quantum transport problem is The idea of quantum computing is to associate a bit to a two-state quantum phenomenon (a “qu-bit”), s
  3 KB (432 words) - 14:14, 23 June 2021
• NVDLA meets PULP
  [[File:nvdla_memory.png|right|NVDLA Memory System and High-Level Architecture]] in terms of performance, area, and power consumption. This includes getting familiar with NVDLA, un
  6 KB (799 words) - 13:42, 10 November 2020
• Heroino: Design of the next CORE-V Microcontroller
  ***Shared, banked, memory for high-performance memory access by both the instruction and the data ports of CV32. ...s]] [[Category:Master Thesis]] [[Category:Hot]][[Category:High Performance Computing]][[Category:FPGA & Digital ASIC Design]][[Category:Embedded systems]][[Cate
  9 KB (1,314 words) - 00:01, 7 February 2021
• Manycore System on FPGA (M/S/G)
  [[Category:High Performance SoCs]] In a quest for high-performance computing systems, few architectural models retain the flexibility of many-core syste
  8 KB (1,319 words) - 10:41, 6 July 2021
• Hardware Acceleration
  ...erators are not limited to the high-performance sector alone. In low power computing, they allow complex tasks such as computer vision or cryptography to be per ==General-Purpose Computing==
  7 KB (917 words) - 17:04, 24 November 2023
• Finite element modeling of electrochemical random access memory
  ...of finite element modeling of electrochemical devices for analog computing. The work will be carried out in the Science & Technology Department at ...RAM operation and the influence of materialspropertiesand geometry on performance metrics requires a detailed multiphysics model
  4 KB (515 words) - 17:06, 16 September 2021
• Implementation of Computationally Efficient Scattering Mechanisms for Periodic Devices and 2D Materials
  ..., which are 3D components that can be approximated as 2D slices, where the high dimension can be High Performance Computing is advantageous but not necessary.
  2 KB (327 words) - 17:06, 16 September 2021
• Event-Driven Convolutional Neural Network Modular Accelerator
  ...ed approaches seem to go into the direction of a higher Sensor Activity to Computing Energy proportionality, which could bring significant advantages to many ed ...igurable in the type of neuron model to use, and in the number of physical computing engines instantiated. The accelerator operations are orchestrated by an RIS
  4 KB (651 words) - 19:10, 29 January 2021
• Toward hyperdimensional active perception: learning compressed sensorimotor control by demonstration
  [[Category:Herschmi]][[Category:Event-Driven Computing]] ...your goal would be to improve algorithms, and implementations based on HD computing
  2 KB (308 words) - 20:12, 9 February 2020
• Spiking Neural Network for Autonomous Navigation
  ...pproach, and seems to go into the direction of a higher Sensor Activity to Computing Energy proportionality, which could bring significant advantages to many ed 1. Study the SNN computing paradigm, and select a population of SNN candidate for the target task
  4 KB (644 words) - 19:10, 29 January 2021
• Semi-Custom Digital VLSI for Processing-in-Memory
  ...eless communication, where massive amounts of data need to be processed at high rates. [[Category:Event-Driven Computing]]
  7 KB (882 words) - 14:33, 28 July 2021
• Hyper-Dimensional Computing Based Predictive Maintenance
  Hyperdimensional computing (HDC) is an energy-efficient alternative to ...design the classification schemes using the primitives of hyperdimensional computing. In a second step, the algorithm should be tuned to be portable to an ultra
  5 KB (759 words) - 09:18, 16 September 2021
• Accurate deep learning inference using computational memory
  ...ty limits in terms of performance and power are being reached, alternative computing paradigms are searched for in which computation and storage are collocated. ...nts on phase-change memory chips comprising more than 1 million devices to high-level algorithmic development in a deep learning framework such as TensorFl
  5 KB (628 words) - 12:51, 17 April 2020
• Classification of Evoked Local-Field Potentials in Rat Barrel Cortex using Hyper-dimensional Computing
  ...ion of implantable multielectrode-arrays (MEAs) to record brain signals at high spatio-temporal resolution. Data processing is needed to decode useful info ...omputing with numbers. HDC has proven to be promising for energy-efficient computing applied to biosignal classification [2].
  5 KB (619 words) - 19:58, 10 March 2024
• High Performance SoCs
  ==High-Performance Systems-on-Chip== ...n ever-increasing amount of '''parallel floating-point performance''' from computing systems. Increasingly, such applications must scale across a wide range of
  11 KB (1,337 words) - 10:54, 25 January 2024
• Energy Efficient SoCs
  ...SoC architectures that combine the versatility of parallel general-purpose computing with the energy efficiency of application-specific hardware accelerators.
  3 KB (339 words) - 15:59, 1 November 2023
• Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S)
  In a quest for high-performance computing systems, few architectural models retain the flexibility of many-core syste ...at 500MHz, and the L1 memory can be accessed by any of the cores through a high-throughput interconnection network with a round-trip latency of at most fiv
  8 KB (1,196 words) - 10:41, 6 July 2021
• Practical Reconfigurable Intelligent Surfaces (RIS)
  ...research for fifth-generation (5G) wireless systems and beyond, providing high data rates for all users was one of the key requirements. From now on, the ...e desired signal power and mitigate interference, improving the system’s performance, without the need of extra APs [4].
  8 KB (1,011 words) - 12:25, 16 November 2023
• Hypervisor Extension for Ariane (M)
  [[Category:High Performance SoCs]] ...ing systems (OSes) – a common technique used in secure systems and cloud computing to allow running untrusted OSes or multiple OSes in parallel.
  3 KB (391 words) - 08:49, 21 June 2022
• Matheus Cavalcante
  * High-Performance Computing
  890 bytes (104 words) - 18:33, 8 December 2020
• Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S)
  [[Category:High Performance SoCs]] Much of our recent work on high-performance computing systems at IIS uses the ''Snitch'' cluster [[#ref-snitch|[3]]]. Thi
  11 KB (1,602 words) - 15:19, 9 July 2021
• A Snitch-Based SoC on iCE40 FPGAs (1-2S/B)
  [[Category:High Performance SoCs]] ...lerator interface, allowing it to be paired with a powerful FPU to achieve high FPU utilizations and compute-over-control ratio.
  8 KB (1,220 words) - 15:18, 9 July 2021
• LLVM and DaCe for Snitch (1-2S)
  [[Category:High Performance SoCs]] ...system [[#ref-zaruba2020snitch|[1]]] targets energy-efficient high-performance systems. It is built around the minimal RISC-V Snitch core, only 15 kGE in
  11 KB (1,519 words) - 15:20, 9 July 2021

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