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• High Performance SoCs
  | style="padding: 10px" | [[File:Colluca picture.png|frameless|left|96px]] ===[[:User:Colluca| Luca Colagrande]]===
  11 KB (1,337 words) - 10:54, 25 January 2024
• Accelerating Stencil Workloads on Snitch using ISSRs (1-2S/B)
  [[Category:Colluca]] ** [[:User:Colluca | Luca Colagrande]]: [mailto:colluca@iis.ee.ethz.ch colluca@iis.ee.ethz.ch]
  3 KB (431 words) - 22:29, 19 January 2023
• Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
  [[Category:Colluca]] ** [[:User:Colluca | Luca Colagrande]]: [mailto:colluca@iis.ee.ethz.ch colluca@iis.ee.ethz.ch]
  7 KB (944 words) - 10:47, 25 January 2024
• GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S)
  [[Category:Colluca]] ** [[:User:Colluca | Luca Colagrande]]: [mailto:colluca@iis.ee.ethz.ch colluca@iis.ee.ethz.ch]
  8 KB (1,186 words) - 11:49, 13 March 2024
• A reduction-capable AXI XBAR for fast M-to-1 communication (1M)
  [[Category:Colluca]] ** [[:User:Colluca | Luca Colagrande]]: [mailto:colluca@iis.ee.ethz.ch colluca@iis.ee.ethz.ch]
  8 KB (1,177 words) - 11:45, 13 March 2024
• A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S)
  [[Category:Colluca]] ** [[:User:Colluca | Luca Colagrande]]: [mailto:colluca@iis.ee.ethz.ch colluca@iis.ee.ethz.ch]
  7 KB (960 words) - 14:25, 2 May 2024
• Accelerating Matrix Multiplication on a 216-core MPSoC (1M)
  [[Category:Colluca]] ** [[:User:Colluca | Luca Colagrande]]: [mailto:colluca@iis.ee.ethz.ch colluca@iis.ee.ethz.ch]
  6 KB (848 words) - 14:25, 2 May 2024
• Efficient collective communications in FlooNoC (1M)
  [[Category:Colluca]] ** [[:User:Colluca | Luca Colagrande]]: [mailto:colluca@iis.ee.ethz.ch colluca@iis.ee.ethz.ch]
  6 KB (897 words) - 19:52, 22 February 2024
• A RISC-V ISA Extension for Scalar Chaining in Snitch (M)
  [[Category:Colluca]] ** [[:User:Colluca | Luca Colagrande]]: [mailto:colluca@iis.ee.ethz.ch colluca@iis.ee.ethz.ch]
  7 KB (1,153 words) - 18:58, 21 April 2024