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• Main Page
  * [[Analog| Analog and Mixed Signal Design]] * [[Design of a D-Band Variable Gain Amplifier for 6G Communication]]
  5 KB (537 words) - 15:22, 23 February 2024
• Template
  : 40% ASIC Design * '''[[Design Review]]'''
  4 KB (397 words) - 15:44, 14 February 2023
• Adaptively Controlled Polarization And Hysteresis Curve Tracing For Polymer Piezoelectrics (1 S/B)
  ...'' for polarization and testing of piezoelectric polymers. It also aims to design the digital architecture in such a way that later studies will allow '''ML- : Analog Mixed Signal Design
  6 KB (741 words) - 18:14, 21 July 2023
• Hybrid Analog/Digital Leveling Loop for Very-Low-Distortion Oscillator
  ...distortion) and noise is necessary. For state-of-the-art resolution, fully analog RC oscillators are required. To stabilize their amplitude, a leveling loop : Interest in high-performance mixed signal circuit design;
  2 KB (307 words) - 20:06, 17 February 2015
• Audio DAC Conversion Jitter Measurement System
  : Interest in high-performance mixed signal circuit design : Experience in analog circuit design beneficial
  2 KB (251 words) - 20:06, 17 February 2015
• Analog
  = Analog and Mixed Signal Design Group = The Analog and Mixed Signal Design Group is specialized in designing mixed signal integrated circuits and systems. The group divides into following re
  3 KB (369 words) - 18:11, 1 March 2023
• Ultra-High-Efficiency Power Supply Management for Ultra-Low-Power Systems on Chip
  ...ion should also serve as evaluation platform for a later mixed-signal ASIC design. : Some experience in circuit design with discrete active and passive components.
  3 KB (438 words) - 18:06, 3 February 2015
• Receiver design for the DigRF 4G high speed serial link
  The task of this project is to design the receiver front-end architecture of a serial DigRF4G link. This standard : Analog Integrated Circuits
  1 KB (197 words) - 17:37, 21 December 2017
• PULPonFPGA: Lightweight Virtual Memory Support - Software Cache
  ...ny-core accelerators into embedded heterogeneous SoCs. We have developed a mixed hardware/software solution to enable lightweight virtual memory support for : ... Design and implement your own software cache suitable for the heterogeneous platfo
  5 KB (716 words) - 13:43, 29 November 2019
• PULPonFPGA: Lightweight Virtual Memory Support - Coherency Extensions
  ...ver module running on the host, our solution features a considerably lower design complexity compared to conventional input/output memory management units (I This system design project requires work to be done at several layers of abstraction. More pre
  4 KB (585 words) - 17:57, 7 November 2017
• PULPonFPGA: Lightweight Virtual Memory Support - Multi-Level TLB
  ...ver module running on the host, our solution features a considerably lower design complexity compared to conventional input/output memory management units (I : ... Implement the selected design in hardware by extending the current design.
  4 KB (554 words) - 17:57, 7 November 2017
• Switched Capacitor Based Bandgap-Reference
  ...re important building blocks in analog and mixed-signal integrated circuit design. The classical Band Gap-Reference combines the negative VBE temperature coe ...is offers the possibility to study main aspects of analog and mixed-signal design, such as noise, linearity, matching, small signal-concepts and power consum
  4 KB (471 words) - 11:13, 3 May 2018
• Compressed Sensing for Wireless Biosignal Monitoring
  ...//asic.ee.ethz.ch/2014/CerebroV4.0_Homer.html] including analog front-end, analog-to-digital conversion, digital signal processing and a compressed sensing e This project may be extended to include the design of a digital ASIC (Application Specific Integrated Circuit) or the implemen
  2 KB (353 words) - 08:35, 20 January 2021
• Low Power Neural Network For Multi Sensors Wearable Devices
  ...ly monitoring the sensor signal. Circuit usually operates in the analog or mixed signal domain, and provides a coarse recognition of some pattern related to ...ise etc.) MEMS microphone is used as an signal input. Prototype implements analog-domain spectral decomposition using multiple band-pass filtering banks. Fre
  7 KB (895 words) - 17:02, 28 July 2017
• PULPonFPGA: Hardware L2 Cache
  ...ny-core accelerators into embedded heterogeneous SoCs. We have developed a mixed hardware/software solution to enable lightweight virtual memory support for ...mplementation on the Xilinx Virtex-7 FPGA but if desired, an ASIC back-end design can also be implemented.
  5 KB (711 words) - 10:27, 5 November 2019
• PULPonFPGA: Lightweight Virtual Memory Support - Page Table Walker
  ...ny-core accelerators into embedded heterogeneous SoCs. We have developed a mixed hardware/software solution to enable lightweight virtual memory support for : 20% VHDL/System Verilog, FPGA Design
  5 KB (712 words) - 17:57, 7 November 2017
• PULPonFPGA: Lightweight Virtual Memory Support - Physically Contiguous Memory
  ...ny-core accelerators into embedded heterogeneous SoCs. We have developed a mixed hardware/software solution to enable lightweight virtual memory support for [[Category:System Design]]
  6 KB (866 words) - 13:43, 29 November 2019
• Charging System for Implantable Electronics
  Using mixed-signal SoCs developed at IIS it is possible to integrate a system to : Experience with hardware design and embedded software
  3 KB (366 words) - 13:05, 27 April 2018
• On-chip clock synthesizer design and porting
  ...endent subsystems (e.g., different processor cores, hardware accelerators, analog IPs, etc), each with its own clocking requirements. All-digital frequency-l ...built and successfully tested various generations of a low-complexity FLL design in different technologies including 65nm and 28nm CMOS technologies.
  3 KB (389 words) - 11:20, 14 September 2016
• BigPULP: Multicluster Synchronization Extensions
  : a mixed hardware/software solution enabling lightweight, shared virtual memory (SVM : 50% Implementation (VHDL, FPGA/ASIC Design, C)
  6 KB (805 words) - 12:17, 22 January 2018

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