Difference between revisions of "User:Colluca"
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| − | I received my B.Sc. from Politecnico di Milano in Electronics Engineering and my M.Sc. in Electrical Engineering from ETH Zürich in 2018 and 2020, respectively. I am currently pursuing a Ph.D. degree under the Digital Circuits and Systems group of Prof. Luca Benini. | + | I received my B.Sc. from Politecnico di Milano in Electronics Engineering and my M.Sc. in Electrical Engineering from ETH Zürich in 2018 and 2020, respectively. I am currently pursuing a Ph.D. degree under the Digital Circuits and Systems group of Prof. Dr. Luca Benini. |
Before starting my Ph.D. I worked for a year in a startup specializing in the design of DNN accelerators exploiting sparsity in weights and activations. | Before starting my Ph.D. I worked for a year in a startup specializing in the design of DNN accelerators exploiting sparsity in weights and activations. | ||
Revision as of 01:28, 12 October 2022
Contents
Luca Colagrande
I received my B.Sc. from Politecnico di Milano in Electronics Engineering and my M.Sc. in Electrical Engineering from ETH Zürich in 2018 and 2020, respectively. I am currently pursuing a Ph.D. degree under the Digital Circuits and Systems group of Prof. Dr. Luca Benini.
Before starting my Ph.D. I worked for a year in a startup specializing in the design of DNN accelerators exploiting sparsity in weights and activations.
My research interests revolve around:
- Energy-efficient and high-performance SoCs
- Fast offloading and synchronization in massively-parallel heterogeneous MPSoCs
- CNN compression algorithms
Contact
- e-mail: colluca@iis.ee.ethz.ch
- whatsapp: +41 779 85 87 89
- phone: +39 375 687 1945
- office: ETZ J89
Projects
Available Projects
- Accelerating Stencil Workloads on Snitch using ISSRs (1-2S/B)
- Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
Projects In Progress
- GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S)
- A RISC-V ISA Extension for Scalar Chaining in Snitch (M)
- Efficient collective communications in FlooNoC (1M)
- A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S)
- Accelerating Matrix Multiplication on a 216-core MPSoC (1M)
