Difference between revisions of "User:Colluca"
From iis-projects
(Created page with "=Luca Colagrande= thumb | 200px| I received my B.Sc. from Politecnico di Milano in Electronics Engineering and my M.Sc. in Electrical Engineer...") |
(→Luca Colagrande) |
||
(13 intermediate revisions by the same user not shown) | |||
Line 3: | Line 3: | ||
[[File:Colluca_picture.png | thumb | 200px|]] | [[File:Colluca_picture.png | thumb | 200px|]] | ||
− | I received my B.Sc. from Politecnico di Milano in Electronics Engineering and my M.Sc. in Electrical Engineering from ETH Zürich in 2018 and 2020, respectively. I am currently pursuing a Ph.D. degree under the Digital Circuits and Systems group of Prof. Luca Benini. | + | I received my B.Sc. from Politecnico di Milano in Electronics Engineering and my M.Sc. in Electrical Engineering from ETH Zürich in 2018 and 2020, respectively. I am currently pursuing a Ph.D. degree under the Digital Circuits and Systems group of Prof. Dr. Luca Benini. |
Before starting my Ph.D. I worked for a year in a startup specializing in the design of DNN accelerators exploiting sparsity in weights and activations. | Before starting my Ph.D. I worked for a year in a startup specializing in the design of DNN accelerators exploiting sparsity in weights and activations. | ||
Line 9: | Line 9: | ||
My research interests revolve around: | My research interests revolve around: | ||
* Energy-efficient and high-performance SoCs | * Energy-efficient and high-performance SoCs | ||
− | * Fast offloading and | + | * Fast and scalable offloading, synchronization and collective communications in massively-parallel heterogeneous MPSoCs |
− | * | + | * Hardware-software co-design at the micro-architecture level |
==Contact== | ==Contact== | ||
Line 17: | Line 17: | ||
* '''whatsapp''': +41 779 85 87 89 | * '''whatsapp''': +41 779 85 87 89 | ||
* '''phone''': +39 375 687 1945 | * '''phone''': +39 375 687 1945 | ||
− | * '''office''': | + | * '''office''': OAT U21 |
==Projects== | ==Projects== | ||
− | ===Available Projects=== | + | ====Available Projects==== |
<DynamicPageList> | <DynamicPageList> | ||
category = Available | category = Available | ||
category = Colluca | category = Colluca | ||
− | |||
ordermethod=sortkey | ordermethod=sortkey | ||
order=ascending | order=ascending | ||
</DynamicPageList> | </DynamicPageList> | ||
− | ===Projects In Progress=== | + | ====Projects In Progress==== |
<DynamicPageList> | <DynamicPageList> | ||
category = In progress | category = In progress | ||
category = Colluca | category = Colluca | ||
− | |||
</DynamicPageList> | </DynamicPageList> | ||
− | ===Completed Projects=== | + | ====Completed Projects==== |
<DynamicPageList> | <DynamicPageList> | ||
category = Completed | category = Completed | ||
category = Colluca | category = Colluca | ||
− | |||
</DynamicPageList> | </DynamicPageList> |
Latest revision as of 21:33, 22 February 2024
Contents
Luca Colagrande
I received my B.Sc. from Politecnico di Milano in Electronics Engineering and my M.Sc. in Electrical Engineering from ETH Zürich in 2018 and 2020, respectively. I am currently pursuing a Ph.D. degree under the Digital Circuits and Systems group of Prof. Dr. Luca Benini.
Before starting my Ph.D. I worked for a year in a startup specializing in the design of DNN accelerators exploiting sparsity in weights and activations.
My research interests revolve around:
- Energy-efficient and high-performance SoCs
- Fast and scalable offloading, synchronization and collective communications in massively-parallel heterogeneous MPSoCs
- Hardware-software co-design at the micro-architecture level
Contact
- e-mail: colluca@iis.ee.ethz.ch
- whatsapp: +41 779 85 87 89
- phone: +39 375 687 1945
- office: OAT U21
Projects
Available Projects
- Accelerating Stencil Workloads on Snitch using ISSRs (1-2S/B)
- Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
Projects In Progress
- GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S)
- A RISC-V ISA Extension for Scalar Chaining in Snitch (M)
- Efficient collective communications in FlooNoC (1M)