Difference between revisions of "User:Cykoenig"
From iis-projects
(→Cyril Koenig) |
|||
| (5 intermediate revisions by the same user not shown) | |||
| Line 5: | Line 5: | ||
==Contact== | ==Contact== | ||
| − | * '''e-mail''': [mailto:cykoenig@iis.ee.ethz.ch | + | * '''e-mail''': [mailto:cykoenig@iis.ee.ethz.ch cykoenig@iis.ee.ethz.ch] |
<!-- * '''phone''': +41 44 632 81 49 --> | <!-- * '''phone''': +41 44 632 81 49 --> | ||
* '''office''': ETZ J76.2 | * '''office''': ETZ J76.2 | ||
| Line 11: | Line 11: | ||
==Research== | ==Research== | ||
| − | [[ | + | [[High Performance SoCs]] |
| − | [[ | + | |
| + | [[Heterogeneous SoCs]] | ||
==Projects== | ==Projects== | ||
Latest revision as of 09:43, 12 April 2024
Contents
Cyril Koenig
Contact
- e-mail: cykoenig@iis.ee.ethz.ch
- office: ETZ J76.2
Research
Projects
Available Projects
- Benchmarking RISC-V-based Accelerator Cards for Inference (multiple SA)
- Benchmarking a RISC-V-based Server on LLMs/Foundation Models (SA or MA)
- Extending the HERO RISC-V HPC stack to support multiple devices on heterogeneous SoCs (M/1-3S)
- Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
Projects In Progress
- Writing a Hero runtime for EPAC (1-3S/B)
- Building an RTL top level for a Mempool-based Heterogeneous SoC (M/1-3S)
Completed Projects
- Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
- A Flexible FPGA-Based Peripheral Platform Extending Linux-Capable Systems on Chip (1-3S/B)
Archived
