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= Overview =
 
= Overview =
  
== Status: Available ==
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== Status: Reserved ==
  
 
* Type: Semester or Bachelor Thesis
 
* Type: Semester or Bachelor Thesis

Revision as of 10:15, 21 January 2022


Overview

Status: Reserved

Introduction

In many computer systems, both in embedded as well as full server systems, Watchdog Timers (WDT) are an essential safety feature, used to detect and correct malfunctions. Typically, a WDT resets an entire system once a counter expires, and to avoid this a properly running system will interfere and set the counter back to its original value (service the WDT). Should a fault in the system occur, either due to a hardware or software malfunction, the WDT will not be properly serviced, resulting in the system returning to its original state.

Project

Goal of this project is to implement a Watchdog Timer (WDT) for a PULP processor core. While a preliminary specification from RISC-V is available, a few additional features should be implemented, such as triggering an interrupt prior to expiration (2-stage WDT), as well as properly disabling the WDT while debugging.

Project structure:

  • Familiarization with the PULP ecosystem, research on other WDT implementations & features
  • Work out an internal guiding specification for the WDT (together with supervisors)
  • Implement a WDT in hardware, integrate it into a PULPissimo SoC
  • Properly verify the WDT, both with regular testbenches as well as software tests in the PULPissimo SoC

Character

  • 10% Literature Review
  • 70% Hardware Design
  • 10% Software Design
  • 10% Evaluation & Documentation

Prerequisites

  • Strong interest in computer architecture
  • Experience with digital design in SystemVerilog as taught in VLSI I

References