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An FPGA-Based Evaluation Platform for Mobile Communications

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Short Description

In this project you will implement a simulation environment for mobile communication receivers on an FPGA.


All parts of a wireless receiver have to be carefully optimized in order to guarantee optimal performance. This is especially true for the word-widths of the signals in an implementation. Often, the word-width of every signal is individually tweaked for an optimal trade-off between performance loss and area and power consumption. However, this requires many time-consuming fixed-point simulations to make sure the performance loss is acceptable.

In this project you will implement a simulation environment on a high-end FPGA board to speed up these simulations. The evaluation of communication algorithms (and decoders in particular) is always similar: + Generate random data (bits) + Code and modulate + [optional: multipath channel] + Add noise + Receiver/Decoder (Model under Test) + Calculate bit error rate (BER) All of this can be done on an FPGA, therefore greatly accelerating the simulation speed compared to a MATLAB-based implementation. The hardware model for the decoder ASIC can easily be transferred to an FPGA. The task of this project will be do implement the simulation environment on both the FPGA (random number generation, encoder and BER calculation) as well as on the PC (communication with the FPGA, plotting of the results). Several decoders have already been implemented in previous IIS projects and will be provided to test the setup.

Status: Available

Looking for 1-2 Semester students
Contact: Sandro Belfanti


MATLAB and VHDL is an advantage


65% VHDL / FPGA implementation
20% MATLAB implementation
15% Testing


Qiuting Huang