FPGA

In an FPGA (Field Programmable Gate Array) Project you will be implementing a digital project using a development board that houses a programmable FPGA and a series of peripherals. Such projects allow you to quickly realize prototypes and/or testbeds used to simulate the behavior of large systems. In such a project you will

• Learn how to program the FPGA board
• Understand the different available peripherals on your system board
• Develop your architecture using Hardware Description Languages (HDL) such as Verilog or VHDL
• Run your system on the development board and collect the results.

Available Projects

• Design of an Ultra-Reliable Low-Latency Modem
• LightProbe - 200G Remote DMA for GPU FPGA Data Transfers
• Machine Learning-based Compressive Sensing Vehicle Location Tracking ASIC Design
• Digital Front End Design & Frequency Offset Estimation for V2X Communications
• High-Throughput Channel Coding & Decoding for V2X Communications
• High-Speed Channel Estimation & Tracking for V2X Communications
• Physics is looking for PULP
• OTDOA Positioning for LTE Cat-M
• High Speed FPGA Trigger Logic for Particle Physics Experiments
• Real-Time Implementation of Quantum State Identification using an FPGA
• Resilient Brain-Inspired Hyperdimensional Computing Architectures
• Autoencoder Accelerator for On-Chip Semi-Supervised Learning
• VLSI Implementation Polar Decoder using High Level Synthesis
• Convolution Neural Networks on our Ultra-Low Power Mult-Core Plattform PULP
• Compressed Sensing for Wireless Biosignal Monitoring
• Compressed Sensing vs JPEG
• Hardware Accelerator for Model Predictive Controller

Projects in Progress

• Next Generation Synchronization Signals
• A Snitch-based Compute Accelerator for HERO (M/1-2S)
• A Flexible Peripheral System for High-Performance Systems on Chip (M)
• Channel Estimation for 5G Cellular IoT and Fast Fading Channels
• Advanced 5G Repetition Combining

Completed Projects

• Energy-Efficient Brain-Inspired Hyperdimensional Computing
• Ibex: FPGA Optimizations
• Timing Channel Mitigations for RISC-V Cores
• HERO: TLB Invalidation
• Indoor Positioning with Bluetooth
• Deep Learning for Brain-Computer Interface
• Turbo Equalization for Cellular IoT
• Shared Correlation Accelerator for an RF SoC
• IoT Turbo Decoder
• BigPULP: Shared Virtual Memory Multicluster Extensions
• Efficient NB-IoT Uplink Design
• BigPULP: Multicluster Synchronization Extensions
• Smart Virtual Memory Sharing
• Hardware Accelerated Derivative Pricing
• Internet of Things Network Synchronizer
• PULPonFPGA: Lightweight Virtual Memory Support - Page Table Walker
• Accelerator for Boosted Binary Features
• Accelerator for Spatio-Temporal Video Filtering
• WCDMA/HSPA+ Synchronization System Design, Implementation, and Testing
• Interfacing PULP with a Brain-Inspired Ultra-Low Power Spiking Cochlea
• System Analysis and VLSI Design of NB-IoT Baseband Processing
• High-speed Scene Labeling on FPGA
• PULPonFPGA: Lightweight Virtual Memory Support - Multi-Level TLB
• High-Throughput Hardware Implementations of Authenticated Encryption Algorithms
• Digital Transmitter for Mobile Communications
• FPGA-Based Digital Frontend for 3G Receivers
• Spatio-Temporal Video Filtering
• PULPonFPGA: Lightweight Virtual Memory Support - Coherency Extensions
• FFT-based Convolutional Network Accelerator
• Synchronisation and Cyclic Prefix Handling For LTE Testbed
• An FPGA-Based Testbed for 3G Mobile Communications Receivers
• Baseband Meets CPU
• Active-Set QP Solver on FPGA
• Vector Processor for In-Memory Computing