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Digital Audio Interface for Smart Intensive Computing Triggering

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Introduction

The ultimate goal of IoT sensor nodes is to collect data and classify them in order to extract high level information. Conventional machine learning algorithms and more recent deep learning-based applications have already achieved very promising results in this direction. The drawback in such applications is that, to achieve reasonably good classification accuracies, the computational effort is often very high, and must be supported at hardware level by powerful processors very often equipped with dedicated accelerators. A very promising approach to avoid wasting power in processing meaningless data (e.g. when just noise is coming from a sensor) is to adopt a hierarchical approach to wake up the different sub-systems of a SoC.

Project description

The main goal of this project is to design a smart digital interface capable to receive data from an audio source (both standard low-power audio front-ends and brain-inspired sensors [adimauro]) and to detect if it contains meaningful information. The advantage of using this infrastructure is that a more intensive downstream processing is triggered only when necessary, avoiding useless energy consumption.

Required Skills

To work on this project, you will need:

  • to have worked in the past with at least one RTL language (SystemVerilog or Verilog or VHDL) - having followed the VLSI1 / VLSI2 courses is recommended
  • basic familiarity with a scripting language for deep learning (Python or Lua…)
  • a lot of patience!
  • to be strongly motivated for a difficult but super-cool project

If you want to work on this project, but you think that you do not match some the required skills, we can give you some preliminary exercise to help you fill in the gap.

Status: In progress

Supervision: Alfio Di Mauro
Supervision: Francesco Conti

Professor

Luca Benini

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Practical Details

Meetings & Presentations

The students and advisor(s) agree on weekly meetings to discuss all relevant decisions and decide on how to proceed. Of course, additional meetings can be organized to address urgent issues.

Around the middle of the project there is a design review, where senior members of the lab review your work (bring all the relevant information, such as prelim. specifications, block diagrams, synthesis reports, testing strategy, ...) to make sure everything is on track and decide whether further support is necessary. They also make the definite decision on whether the chip is actually manufactured (no reason to worry, if the project is on track) and whether more chip area, a different package, ... is provided. For more details confer to [1].

At the end of the project, you have to present/defend your work during a 15 min. presentation and 5 min. of discussion as part of the IIS colloquium.


Literature

[adimauro] A. Di Mauro, F. Conti and L. Benini, "An ultra-low power Address-Event sensor interface for energy-proportional time-to-information extraction," 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC), Austin, TX, 2017, pp. 1-6. doi: 10.1145/3061639.3062201

Links

  • The EDA wiki with lots of information on the ETHZ ASIC design flow (internal only) [2]
  • The IIS/DZ coding guidelines [3]↑ top