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Standard Cell Compatible Memory Array Design

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Short Description

Standard Cell Compatible Memory Array Design.png

Memories are central building blocks of any processing system, in fact most of the performance of a modern processor is determined by its ability to efficiently store and retrieve data. For IC design, we usually rely on memory generators provided by standard cell vendors to generate SRAM macro-blocks. These generators are designed to provide good density (more bits per area) for the most commonly used memory sizes. Depending on the technology, there might be more than one generator that is able to generate memories with different goals (smaller area, faster access time) and are suitable for a different range of memories (i.e. for memories with 1024 to 8192 rows). Currently none of these memory generators we have access to, deliver competitive results for smaller memories (16 to 64 words of 8 to 128 bits) especially for ultra-low-power domain where low-voltage operation is paramount. These smaller memories are frequently used as part of the instruction cache, as a register file or as FIFO buffers between clock domain crossings in our recent PULP projects.


As a result, we have started investigating so called standard cell based memories (SCM). These are built using latches multiplexers and clock gating cells that form part of every standard cell library. By combining these, we can actually generate small memories that are better than those that could be generated by the SRAM macros we have access to. The SCMs end up being a regular part of the netlist, and can be placed and routed in the design flow like regular standard cells along with the rest of the circuit.

Our Goal

We believe that we can do even better than that. In this project we would like to explore the possibility to make dedicated small memory arrays that are optimized for low-power operation and are compatible with the standard cell grid allowing them to be placed and routed without additional overhead (similar to SCMs). But unlike SCMs we want the generator to build macro cells that are already placed, routed and characterized.

A typical memory has four different parts:

  1. a storage cell that keeps the information
  2. the decoding logic that activates one row of the memory at a time
  3. the readout circuit that reads out the data from the array
  4. a write circuitry that allows the content of the cell to be modified.

There are multiple solutions for all four parts that have been studied. In this work we will put together we will investigate and put together the most efficient solutions in one custom generator. The goal would be to target memories up to maximum 64 words with bit widths of 8 up to 256 with 8 bit increments. Limiting the size to these will enable us to optimize the arrays even more. Whenever possible we would like to make sure that the memories work at the lowest operating voltage possible. In the later stages of the design we would like to also investigate more advanced power saving features, like body biasing and power gating all or sections of the memory array.

In addition we want to have the following features:

  • Sharing clock drivers and gating cells across several storage cells to reduce area/power overhead
  • Automatically generating LEF/LIB files necessary for the backend integration.
  • Making sure that there is no additional overhead in the backend flow, making sure that the edges of the generated macro aligns well with the rest of the standard cell based design.
  • The possibility to add multiple ports for read and write
  • Adding scan functionality to the input and output allowing the circuits placed outside the memory to be tested regularly
  • Adapting a built-in self-test methodology for the array itself

We believe that this project can deliver the most efficient small memory generator available to us, and beat the performance of what we can achieve with standard SRAM generators and SCMs. As such, if successful, this project will play a central role in our upcoming PULP projects.

Status: In Progress

Fabian Schuiki
Supervision: Frank K. Gurkaynak Florian Glaser


Luca Benini


30% Full custom design
50% Toolflow Integration
20% Implement state retentive power gating in existing design


  • Knowledge of digital circuit design
  • Basic knowledge of the backend design flow for IC design (i.e VLSI2)
  • Familiarity with transistor level design is a plus, but is not necessary (i.e AIC)


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