Difference between revisions of "Robert Balas"
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==Contact== | ==Contact== | ||
* Office: ETZ J85 | * Office: ETZ J85 | ||
Revision as of 21:08, 18 November 2021
Contact
- Office: ETZ J85
- E-Mail: balasr@iis.ee.ethz.ch
- Phone: +41 44 632 42 56
Interests
- Processor Design
- Real-Time/Predictability
- Operating Systems
- Compilers
Projects
Available Projects
- Designing a Fault-Tolerant On-Chip Interconnect (1-2S/M)
- Enhancing our DMA Engine with Fault Tolerance
- Scan Chain Fault Injection in a PULP SoC (1S)
- Towards Formal Verification of the iDMA Engine (1-3S/B)
Projects In Progress
- Designing a Scalable Miniature I/O DMA (1-2B/1-3S/M)
- Fault-Tolerant Floating-Point Units (M)
- Creating a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B)
- Implementation of a Cache Reliability Mechanism (1S/M)
- On-Board Software for PULP on a Satellite
- A RISC-V fault-tolerant many-core accelerator for 5G Non-Terrestrial Networks (1-2S/B)
- Radiation Testing of a PULP ASIC
Completed Projects
- Extension and Evaluation of TinyDMA (1-2S/B/2-3G)
- Design of an Area-Optimized Soft-Error Resilient Processing Core for Safety-Critical Systems (1M)
- MCU Bus and Memory Generator: implementation of a Highly Configurable bus and memory subsystem for a RISC-V based microcontroller.
- Implementing Configurable Dual-Core Redundancy
- Running Rust on PULP
- Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B)
- Adding Linux Support to our DMA Engine (1-2S/B)
- Triple-Core PULPissimo
- Watchdog Timer for PULP
- Hypervisor Extension for Ariane (M)
