A RISC-V fault-tolerant many-core accelerator for 5G Non-Terrestrial Networks (1-2S/B)

Overview

Status: In progress

• Type: Bachelor or Semester Thesis
• Professor: Prof. Dr. L. Benini
• Supervisors:
  • Marco Bertuletti: mbertuletti@iis.ee.ethz.ch
  • Michael Rogenmoser: michaero@iis.ee.ethz.ch

Introduction

In the fully connected world of 5G and 6G telecommunications, Non-Terrestrial Networks represent a challenging problem, as they require strict latency and throughput constraints. The hardware that enables such communication infrastructures is exposed to hostile environments, as it must be carried on orbiting satellites. Some kind of fault-tolerance must therefore be foreseen for these systems.

In IIS we have expertise in both fields: we are developing TeraPool, a 1024 cores cluster for 5G telecommunications and we are exploiting fault-tolerance hardware solutions, such as dual-module redundancy and Error Correcting Codes (ECC), to make it fault-tolerant. Our target is to prove that TeraPool is competitive with state-of-the-art solutions for 5G telecommunications in space and we will need your help to optimize and run real-world software on it.

Project

The goal of this project is to run a 5G Non-Terrestrial network on the Many-Core TeraPool cluster, to evaluate the effectiveness of the fault-tolerant hardware implemented on the cluster and to benchmark the performance of the architecture on a real-case scenario, both in terms of throughput-latency performance and of BER.

• You will learn about 5G telecommunications and protocols for Non-Terrestrial Communications.
• You will implement a software processing pipeline in C on TeraPool, gaining expertise in the implementation, scheduling, and parallelization of heterogeneous kernels.
• You will learn about fault-tolerance hardware mechanisms and you will benchmark the hardware-software system in a fault injection simulation environment.

Character

• 20% Literature Review
• 50% Software Design
• 20% Benchmarking
• 10% Documentation

Prerequisites

• Strong interest in computer architecture and signal processing
• Experience in C/C++ programming, OpenMP