User contributions
From iis-projects
- 17:44, 15 August 2022 diff hist +1,047 MCU Bus and Memory Generator: implementation of a Highly Configurable bus and memory subsystem for a RISC-V based microcontroller. →Status: Available
- 17:42, 15 August 2022 diff hist +395 MCU Bus and Memory Generator: implementation of a Highly Configurable bus and memory subsystem for a RISC-V based microcontroller. →Required Skills
- 17:39, 15 August 2022 diff hist +12 MCU Bus and Memory Generator: implementation of a Highly Configurable bus and memory subsystem for a RISC-V based microcontroller. →Project objectives
- 17:39, 15 August 2022 diff hist +1,402 MCU Bus and Memory Generator: implementation of a Highly Configurable bus and memory subsystem for a RISC-V based microcontroller. →Project description
- 17:34, 15 August 2022 diff hist +2,903 MCU Bus and Memory Generator: implementation of a Highly Configurable bus and memory subsystem for a RISC-V based microcontroller. →Introduction
- 17:26, 15 August 2022 diff hist +2,214 N MCU Bus and Memory Generator: implementation of a Highly Configurable bus and memory subsystem for a RISC-V based microcontroller. Created page with "==Introduction== Microcontrollers (MCUs) are used in a wide range of applications ranging from sensor-monitoring all the way to robotics. Despite typically lower in performa..."
- 17:22, 15 August 2022 diff hist +261 User:Pschiavo →Available projects current
- 17:19, 15 August 2022 diff hist -80 User:Pschiavo →Pasquale Davide Schiavone
- 17:08, 15 August 2022 diff hist +158 Energy Efficient SoCs
- 00:01, 7 February 2021 diff hist -16 Heroino: Design of the next CORE-V Microcontroller →Architecture current
- 00:01, 7 February 2021 diff hist 0 N File:Heroino.png current
- 00:00, 7 February 2021 diff hist +52 Heroino: Design of the next CORE-V Microcontroller →Architecture
- 23:59, 6 February 2021 diff hist +98 Heroino: Design of the next CORE-V Microcontroller →Verification
- 23:57, 6 February 2021 diff hist +97 Heroino: Design of the next CORE-V Microcontroller →Status: Available
- 23:54, 6 February 2021 diff hist -39 Heroino: Design of the next CORE-V Microcontroller →Status: Available
- 23:53, 6 February 2021 diff hist -43 Heroino: Design of the next CORE-V Microcontroller →Status: Available
- 23:53, 6 February 2021 diff hist +2,026 Heroino: Design of the next CORE-V Microcontroller →Verification
- 23:51, 6 February 2021 diff hist +3,150 Heroino: Design of the next CORE-V Microcontroller →Architecture
- 23:46, 6 February 2021 diff hist +1,090 Heroino: Design of the next CORE-V Microcontroller →Repo organization
- 23:45, 6 February 2021 diff hist -7 Heroino: Design of the next CORE-V Microcontroller →Repo organization
- 23:45, 6 February 2021 diff hist +57 Heroino: Design of the next CORE-V Microcontroller →Continuous Integration Checks and Artifact generation
- 15:01, 6 February 2021 diff hist +19 Heroino: Design of the next CORE-V Microcontroller →Feature Set
- 14:59, 6 February 2021 diff hist +33 Heroino: Design of the next CORE-V Microcontroller
- 14:56, 6 February 2021 diff hist +2,420 N Heroino: Design of the next CORE-V Microcontroller Created page with "'''Introduction''' The CORE-V MCU serves as a minimal basis to demonstrate the capabilities of the OpenHW Group CORE-V CV32E4 and CVA6 microprocessors, previously known as RI..."
- 14:55, 6 February 2021 diff hist -377 User:Pschiavo →Available projects
- 11:33, 30 August 2019 diff hist -2 Design of Scalable Event-driven Neural-Recording Digital Interface →Status: In progress
- 11:10, 30 August 2019 diff hist +257 Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core →Professor
- 11:09, 30 August 2019 diff hist +258 Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core →Professor
- 10:16, 14 June 2019 diff hist -1,096 User:Pschiavo →Required Skills
- 10:16, 14 June 2019 diff hist +3,873 N Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core Created page with "==Introduction== RISC-V is an open-source Instruction Set Architecture (ISA) governed by the no-profit organization RISC-V (https://riscv.org/). Thanks to its simplicity, effi..."
- 10:16, 14 June 2019 diff hist -537 User:Pschiavo →Project description
- 10:16, 14 June 2019 diff hist -2,240 User:Pschiavo →Introduction
- 10:15, 14 June 2019 diff hist +3,872 User:Pschiavo →Available projects
- 10:14, 14 June 2019 diff hist +1 User:Pschiavo →Available projects
- 10:02, 14 June 2019 diff hist -3 Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RI5CY core →Status: Available
- 10:00, 14 June 2019 diff hist +1,099 Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RI5CY core →Project description
- 09:59, 14 June 2019 diff hist +2,777 N Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RI5CY core Created page with "==Introduction== RISC-V is an open-source Instruction Set Architecture (ISA) governed by the no-profit organization RISC-V (https://riscv.org/). Thanks to its simplicity, effi..."
- 09:55, 14 June 2019 diff hist +113 User:Pschiavo →Available projects
- 12:46, 25 February 2019 diff hist -4 Design of Scalable Event-driven Neural-Recording Digital Interface →Project description
- 15:54, 21 February 2019 diff hist +41 Design of Scalable Event-driven Neural-Recording Digital Interface →Project description
- 17:54, 20 February 2019 diff hist +43 Design of Scalable Event-driven Neural-Recording Digital Interface →Status: In progress
- 17:51, 20 February 2019 diff hist +2 Design of Scalable Event-driven Neural-Recording Digital Interface →Status: Available
- 17:51, 20 February 2019 diff hist +2 Design of Scalable Event-driven Neural-Recording Digital Interface →Status: Available
- 17:51, 20 February 2019 diff hist -46 Design of Scalable Event-driven Neural-Recording Digital Interface →Project description
- 17:50, 20 February 2019 diff hist -16 User:Pschiavo →Contact Information
- 17:49, 20 February 2019 diff hist +135 Design of Scalable Event-driven Neural-Recording Digital Interface →Status: Taken
- 17:48, 20 February 2019 diff hist -778 Design of Scalable Event-driven Neural-Recording Digital Interface →Project description
- 17:37, 20 February 2019 diff hist 0 N File:Spike extraction.png current
- 17:17, 20 February 2019 diff hist +663 Design of Scalable Event-driven Neural-Recording Digital Interface →Introduction