User:Fischeti
From iis-projects
Tim Fischer
I received my Bachelor's degree in Information Technology and Electrical Engineering from Swiss Federal Institute of Technology Zurich (ETHZ), Switzerland in 2018 and my Master's degree in April 2020. After that, I started as a PhD Student in the digital circuits and systems group of Prof. Dr. L. Benini
Interests
My research focuses on interconnects for on-chip and off-chip communication in HPC Systems. Specifically, I am currently working on Network-on-Chips (NoCs) to enable scaling out to manycore systems. Further, I have also worked on a Die-to-Die link for chiplet-based systems.
Previously, I also deployed Machine Learning Workloads on High-Performance Computing systems and worked on ML Hardware Accelerator for edge applications.
Contact Information
- Office: OAT U21
- e-mail: fischeti@iis.ee.ethz.ch
- www: IIS Homepage
Available Projects
- Modeling FlooNoC in GVSoC (S/M)
- Scaleout Study on Interleaved Memory Transfers in Huge Manycore Systems with Multiple HBM Channels (M/1-3S)
- Routing 1000s of wires in Network-on-Chips (1-2S/M)
- Network-on-Chip for coherent and non-coherent traffic (M)
- Energy Efficient AXI Interface to Serial Link Physical Layer
Projects In Progress
No pages meet these criteria.
Completed Projects
- Network-off-Chip (M)
- MCU Bus and Memory Generator: implementation of a Highly Configurable bus and memory subsystem for a RISC-V based microcontroller.
- Design of a Prototype Chip with Interleaved Memory and Network-on-Chip
- Flexfloat DL Training Framework
- A Unified Compute Kernel Library for Snitch (1-2S)
