Modeling FlooNoC in GVSoC (S/M)
From iis-projects
Contents
Overview
Status: Available
- Type: Semester Thesis or Master Thesis
- Professor: Prof. Dr. L. Benini
- Supervisors:
Introduction
GVSoC
GVSoC is a sophisticated, highly configurable, and timing-accurate event-driven simulator designed for simulating IoT processors and complex system-on-chips (SoCs). It plays a crucial role in enabling agile design space exploration for low-power SoCs, particularly useful in scenarios demanding rapid and accurate simulation of heterogeneous systems combining microcontroller units (MCUs) with application-specific accelerators. GVSoC achieves this by combining the efficiency of C++ models with the flexibility of Python configuration scripts, allowing for the simulation of full-platform systems including multicore, multi-memory levels, and various I/O peripherals. Remarkably, GVSoC delivers simulation speeds up to 2500 times faster than cycle-accurate simulators, maintaining errors typically below 10% for performance analysis. This makes it an invaluable tool in breaking the speed and design effort bottlenecks of traditional simulators and FPGA prototypes, while still preserving functional and timing accuracy. [1][2]
FlooNoC
FlooNoC is a modern, open-source Network-on-Chip (NoC) architecture designed in our group [3][4], distinguished for its low-latency, full AXI4 compatibility, and wide physical channels. Designed to address the high-bandwidth requirements of contemporary applications, FlooNoC stands out for its efficient handling of both high-bandwidth, burst-based traffic and latency-critical short messages. The architecture's key elements include scalable and low-complexity routers, wide channels for high bandwidth throughput, and a decoupled link-level protocol for enhanced scalability. It is particularly notable for demonstrating high energy efficiency and a modest area footprint, making it an ideal candidate for integration into advanced SoC designs.
Project
This project seeks to integrate the innovative FlooNoC architecture into the GVSoC simulation framework. The integration aims to leverage GVSoC’s fast, accurate, and highly configurable simulation capabilities to enable fast design space exploration (DSE) compared to slow and cumbersome RTL simulations. This will enhance GVSoC's utility in simulating advanced NoC architectures and contribute to the development of more efficient and scalable SoC designs.
The goals of this projects are the following:
1. Research: Getting familiar with the implementation of GVSoC and how understand the architecture of FlooNoC in order to know how you need to model it in GVSoC. Identify key integration points and challenges.
2. Modeling: Develop a detailed model of FlooNoC within GVSoC, with a good tradeoff of performance and accuracy.
3. Generation: Extend GVSoC with the capability to quickly generate different network topologies to enable quick design space exploration
4. Analysis: Evaluate GVSoC and your model of FlooNoC in terms of performance, accuracy, and usability/
Character
- 20% Literature Research
- 50% Modelling
- 20% Analysis
- 10% Documentation & Report
Prerequisites
- Knowledge in C++ and Python is recommended for developing GVSoC
- Experience with System Verilog is recommended but not strictly necessary
