Category:Available

We are actively searching for students to work on these projects. Please contact the responsible of the project if you are interested or if you have more questions.

Hot Projects

• An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)
• Evaluating An Ultra low Power Vision Node
• Probabilistic training algorithms for quantized neural networks
• Exploring schedules for incremental and annealing quantization algorithms
• VLSI Implementation of a 5G Ciphering Accelerator
• Efficient TNN compression
• Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S)
• Event-Driven Vision on an embedded platform
• Knowledge Distillation for Embedded Machine Learning
• Hardware Constrained Neural Architechture Search
• IBM Research
• Combining Spiking Neural Networks with Hyperdimensional Computing for Autonomous Navigation
• RISC-V based Implementation of Secure Ranging According to IEEE 802.15.4z UWB
• Improved State Estimation on PULP-based Nano-UAVs
• Data Augmentation Techniques in Biosignal Classification
• Compression of iEEG Data
• BCI-controlled Drone
• Contrastive Learning for Self-supervised Clustering of iEEG Data for Epileptic Patients
• Palm size chip NMR probe
• MmWave PLL: 100GHz PLL using reference oversampling scheme
• Deep neural networks for seizure detection
• Spiking Neural Network for Autonomous Navigation
• Event-Driven Convolutional Neural Network Modular Accelerator
• Characterization of the susceptibility to cosmic radiation of wide bandgap power devices by radioactive sources and at cryogenic temperatures
• Design of an on-field adaptable pulse-processing unit for semicondutor radiation detectors
• Design of an Ultra-Reliable Low-Latency Modem
• Towards global Brain-Computer Interfaces
• Electrical characterization and optimization of electrochemical random-access memory for analog computing
• Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core
• Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RI5CY core
• Design and Exploitation of a Test-Bench for Non-Destructive Characterization of the Susceptibility of Silicon Carbide (SiC) Power Devices to Cosmic Radiation
• Experimental Validation of Impact Ionization Models for TCAD Simulation by a Novel Characterization Technique
• Design and implementation of the front-end for a portable ionizing radiation detector
• Level Crossing ADC For a Many Channels Neural Recording Interface
• Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core
• Heart Rate Detection Algorithm
• Optical Weights for Photonic Neural Networks
• Design of key building blocks for miniaturized sensor systems
• Energy Efficient Circuits for Wireless Neural Recording
• Application Specific Frequency Synthesizers (Analog/Digital PLLs)
• Ultra-low power transceiver for implantable devices
• Extend the RI5CY core with priviledge extensions
• Monocular Vision-based Object Following on Nano-size Robotic Blimp
• A Waypoint-based Navigation System for Nano-Size UAVs in GPS-denied Environments
• Design of a 25 Gbps SerDes for optical chip-to-chip communication
• Real-Time Implementation of Quantum State Identification using an FPGA
• Autonomous Sensors For Underwater Monitoring In Smart Navy Systems
• Variable Bit Precision Logic for Deep Learning and Artificial Intelligence
• Towards Online Training of CNNs: Hebbian-Based Deep Learning
• Embedded Audio Source Localization Exploiting Coincidence Detection in Asynchronous Spike Streams
• Autoencoder Accelerator for On-Chip Semi-Supervised Learning
• High performance continuous-time Delta-Sigma ADC for magnetic resonance imaging
• Development of a syringe label reader for the neurocritical care unit
• VLSI Implementation Polar Decoder using High Level Synthesis
• Smart Wearable System For Vital Sign Monitoring Exploiting On Board and Cloud Machine Learning
• Convolution Neural Networks on our Ultra-Low Power Mult-Core Plattform PULP
• Design of Charge-Pump PLL in 28nm for 5G communication applications
• High Performance Digitally-Assisted Time Domain ADC Design for DPLL used in Cellular IOT
• High Power Efficient Digitally Controlled Oscillator Design for Cellular IOT
• PVT Dynamic Adaptation in PULPv3
• Linux Driver for fine-grain and low overhead access to on-chip performance counters
• Open Power-On Chip Controller Study and Integration
• Passive and Self Sustaining Receivers For On and Intra Body Communication For Wearable Sensors Networks
• A Wearable System To Control Phone And Electronic Device Without Hands
• Ultra Low Power Conversion Circuit For Batteryless Applications
• Using Motion Sensors to Support Indoor Localization
• Birds Long Term Monitoring With Ultra Low Power Wireless Sensor Node
• Ab-initio modeling of ballistic thermal transport
• Developing High Efficiency Batteries for Electric Cars
• Processing of 3D Micro-tomography data for Lithium Ion Batteries

Digital Design

• Short Range Radars For Biomedical Application
• An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)
• Smart Patch For Heath Care And Rehabilitation
• Autonomus Drones With Novel Sensors And Ultra Wide Band
• Evaluating memory access pattern specializations in OoO, server-grade cores (M)
• Evaluating An Ultra low Power Vision Node
• Hypervisor Extension for Ariane (M)
• Mapping Networks on Reconfigurable Binary Engine Accelerator
• Probabilistic training algorithms for quantized neural networks
• Exploring schedules for incremental and annealing quantization algorithms
• VLSI Implementation of a 5G Ciphering Accelerator
• Machine Learning on Ultrasound Images
• RISC-V base ISA for ultra-low-area cores (2-3G)
• IP-Based SoC Generation and Configuration (1-3S/B)
• Outdoor Precision Object Tracking for Rockfall Experiments
• Efficient Search Design for Hyperdimensional Computing
• Efficient TNN compression
• SystemVerilog formatter for our LowRISC-based guidelines (2-3G)
• Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S)
• Coherence-Capable Write-Back L1 Data Cache for Ariane (M)
• PREM Runtime Scheduling Policies
• Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S)
• Event-Driven Vision on an embedded platform
• Smart Meters
• Time Gain Compensation for Ultrasound Imaging
• Minimum Variance Beamforming for Wearable Ultrasound Probes
• Machine Learning for extracting Muscle features using Ultrasound
• Knowledge Distillation for Embedded Machine Learning
• Hardware Constrained Neural Architechture Search
• IBM Research
• Combining Spiking Neural Networks with Hyperdimensional Computing for Autonomous Navigation
• RISC-V based Implementation of Secure Ranging According to IEEE 802.15.4z UWB
• Improved State Estimation on PULP-based Nano-UAVs
• Classification of Evoked Local-Field Potentials in Rat Barrel Cortex using Hyper-dimensional Computing
• Data Augmentation Techniques in Biosignal Classification
• Compression of iEEG Data
• BCI-controlled Drone
• Contrastive Learning for Self-supervised Clustering of iEEG Data for Epileptic Patients
• Nanoelectrode array biosensors - programmable non-overlapping clocks generator project
• Real-Time Motor-Imagery Classification Using Neuromorphic Processor
• Accurate deep learning inference using computational memory
• Deep neural networks for seizure detection
• Spiking Neural Network for Autonomous Navigation
• Event-Driven Convolutional Neural Network Modular Accelerator
• Pressure and acoustic Smart Sensors Network for Wind Turbines Monitoring
• Design of an Ultra-Reliable Low-Latency Modem
• Towards global Brain-Computer Interfaces
• Neural Network Algorithms and Interfaces with Accelerators for Embedded Platforms with Real World Applications
• Design Of A Biomarker Assay Based On Responsive Magnetic Nanoparticles
• High-throughput Embedded System For Neurotechnology in collaboration with INI
• Neuromorphic Intelligence In An Embedded System in Collaboration with AiCTX
• Adversarial Attacks Against Deep Neural Networks In Wearable Cameras
• Wearable Smart Camera With Deep Learning Algorithms For Automatic Detecion
• Visualizing Functional Microbubbles using Ultrasound Imaging
• Energy Efficient Smart Devices For Construction Building Maintenance Hilti Collaboration
• Extending the RISCV backend of LLVM to support PULP Extensions
• Compiler Profiling and Optimizing
• PREM Intervals and Loop Tiling
• Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core
• Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RI5CY core
• LightProbe - 200G Remote DMA for GPU FPGA Data Transfers
• Level Crossing ADC For a Many Channels Neural Recording Interface
• Scalable Heterogeneous L1 Memory Interconnect for Smart Accelerator Coupling in Ultra-Low Power Multicores
• Improving Cold-Start in Batteryless And Energy Harvesting Systems
• SmartRing
• Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core
• Machine Learning-based Compressive Sensing Vehicle Location Tracking ASIC Design
• Digital Front End Design & Frequency Offset Estimation for V2X Communications
• High-Throughput Channel Coding & Decoding for V2X Communications
• High-Speed Channel Estimation & Tracking for V2X Communications
• PREM on PULP
• Design and Evaluation of a Small Size Avalanche Beacon
• Edge Computing for Long-Term Wearable Biomedical Systems
• AMZ Driverless Competition Embedded Systems Projects
• Optogenetics And Game Theory Applied To Small Side Bird Using Smart Sensing
• Wireless Sensing With Long Range Comminication (LoRa)
• Indoor Smart Tracking of Hospital instrumentation
• A Wearable Wireless Kidney Function Monitoring System For BioMedical Applications
• Physics is looking for PULP
• Embedded Gesture Recognition Using Novel Mini Radar Sensors
• Contextual Intelligence on Resource-constraint Bluetooth LE IoT Devices
• An Industrial-grade Bluetooth LE Mesh Network Solution
• Enabling Standalone Operation for a Mobile Health Platform
• Design and Implementation of a multi-mode multi-master I2C peripheral
• Optimal System Duty Cycling for a Mobile Health Platform
• OTDOA Positioning for LTE Cat-M
• Extend the RI5CY core with priviledge extensions
• BLISS - Battery-Less Identification System for Security
• Monocular Vision-based Object Following on Nano-size Robotic Blimp
• A Waypoint-based Navigation System for Nano-Size UAVs in GPS-denied Environments
• Zero Power Touch Sensor and Reciever For Body Communication
• Wake Up Radio For Energy Efficient Communication System and IC Design
• A Wireless Sensor Network for HPC monitoring
• High Speed FPGA Trigger Logic for Particle Physics Experiments
• Low Power One bit Microphone for Acoustic Imaging Using A Parallel Processor
• Low Power Geolocalization And Indoor Localization
• Real-Time Implementation of Quantum State Identification using an FPGA
• Neural Networks Framwork for Embedded Plattforms
• Hyper Meccano: Acceleration of Hyperdimensional Computing
• Autonomous Sensors For Underwater Monitoring In Smart Navy Systems
• Resilient Brain-Inspired Hyperdimensional Computing Architectures
• Variable Bit Precision Logic for Deep Learning and Artificial Intelligence
• Autoencoder Accelerator for On-Chip Semi-Supervised Learning
• Autonomous Sensing For Trains In The IoT Era
• VLSI Implementation Polar Decoder using High Level Synthesis
• Smart Wearable System For Vital Sign Monitoring Exploiting On Board and Cloud Machine Learning
• Tiny CNNs for Ultra-Efficient Object Detection on PULP
• Single-Bit-Synapse Spiking Neural System-on-Chip
• OpenRISC SoC for Sensor Applications
• Desing and Implementation Of Long Lasting Key Finder With Bleetooth Low Energy
• Radio Signal Direction Detection For Smart Glasses For Augmented Reality Applications
• PVT Dynamic Adaptation in PULPv3
• Passive and Self Sustaining Receivers For On and Intra Body Communication For Wearable Sensors Networks
• A Wearable System To Control Phone And Electronic Device Without Hands
• Towards The Integration of E-skin into Prosthetic Devices
• Ultra Low Power Conversion Circuit For Batteryless Applications
• Towards Self Sustainable UAVs
• Fast Wakeup From Deep Sleep State
• Using Motion Sensors to Support Indoor Localization
• Low Power Neural Network For Multi Sensors Wearable Devices
• Bateryless Heart Rate Monitoring
• Birds Long Term Monitoring With Ultra Low Power Wireless Sensor Node
• Covariant Feature Detector on Parallel Ultra Low Power Architecture
• Ultra-Efficient Visual Classification on Movidius Myriad2
• Kinetic Energy Harvesting For Autonomous Smart Watches
• A Wearable System for long term monitoring of human physiological parameters with E skin sensors
• Autonomous Smart Watches: Toward an ultra low power microphone detector with events classification
• Autonomous Smart Watches: Hardware and Software Desing
• A Wireless Sensor Network for a Smart LED Lighting control
• Compressed Sensing for Wireless Biosignal Monitoring
• Compressed Sensing vs JPEG
• Ultra-High-Efficiency Power Supply Management for Ultra-Low-Power Systems on Chip
• Real-Time Pedestrian Detection For Privacy Enhancement
• Thermal Control of Mobile Devices
• Android reliability governor
• Infrared Wake Up Radio
• Ambient RF Energy harvesting for Wireless Sensor Network
• ASIC Design of a Sigma Point Processor
• ASIC Design of a Gaussian Message Passing Processor
• Hardware Accelerator for Model Predictive Controller
• Hardware Support for IDE in Multicore Environment
• Audio DAC Conversion Jitter Measurement System
• Hybrid Analog/Digital Leveling Loop for Very-Low-Distortion Oscillator
• Wiederverwendung (reuse) ganzer Funktionsblöcke beim VLSI-Entwurf
• Praxisgerechte Berechnung von Switching Noise in VLSI-Schaltungen
• Ultra Low Power Wake Up Radio for Wireless Sensor Network
• Variability Tolerant Ultra Low Power Cluster

Analog Design

• Event-Driven Convolutional Neural Network Modular Accelerator
• Level Crossing ADC For a Many Channels Neural Recording Interface
• Heart Rate Detection Algorithm
• Enabling Standalone Operation for a Mobile Health Platform
• Design and Implementation of a multi-mode multi-master I2C peripheral
• Ultra-low power transceiver for implantable devices
• Optimal System Duty Cycling for a Mobile Health Platform
• Exploring Bio Impedance
• Inductive Charging Circuit for Implantable Devices
• Design of a 25 Gbps SerDes for optical chip-to-chip communication
• 5G Cellular RF Front-end Design in 28nm CMOS Technology
• High performance continuous-time Delta-Sigma ADC for magnetic resonance imaging
• Design of Charge-Pump PLL in 28nm for 5G communication applications
• High Performance Digitally-Assisted Time Domain ADC Design for DPLL used in Cellular IOT
• High Power Efficient Digitally Controlled Oscillator Design for Cellular IOT
• Android Software Design

Nano Electronics

• Developing High Efficiency Batteries for Electric Cars
• Processing of 3D Micro-tomography data for Lithium Ion Batteries
• Assessment of novel photovoltaic architectures by circuit simulation

Nano-TCAD

• Using piezoelectricity in monolayer 2D materials to build future nanoscale devices
• Source contact engineering in 2D materials MOSFET to achieve sub-60 mV/decade transistors
• Electrical characterization and optimization of electrochemical random-access memory for analog computing
• Finite element modeling of electrochemical random access memory
• Influence of the Initial Filament Geometry on the Forming Step in CBRAM.
• Nanoscale Hybrid III-V Plasmonic Laser for Low-Power Photonic ICs
• Design space exploration of InP Heterojunction Bipolar Transistors (DHBTs)
• Quantum transport in 2D heterostructures
• Optical Weights for Photonic Neural Networks
• Ab-initio modeling of ballistic thermal transport
• Development of an efficient algorithm for quantum transport codes
• Investigation of Metal Diffusion in Oxides for CBRAM Applications
• Investigation of Redox Processes in CBRAM

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