Design of a VLIW processor architecture based on RISC-V
From iis-projects
Short Description
RISC-V is an open source instruction set architecture (ISA) designed by UC Berkeley. For the PULP architecture we have designed our own RISC-V cores which target maximum energy efficiency. The cores are based on an in-order, 4 stage 32b pipeline. However, RISC-V is not only proposing 32b instructions, but also 16b(so-called compressed instructions), 48b, and 64b instructions. Our core is already supporting 16b, and 32b instructions, but as we have an in-order pipeline, the cores can only execute one instruction at the time. Moving to a very long instruction word (VLIW) architecture has several interesting advantages. Assuming a e.g. 48b instruction interface would allow to fetch 2 instructions (1*32b+1*16b) which can be carried out in parallel. (e.g. 1 ALU + 1 LSU instruction)
The tasks of this project are rather challenging as the VLSI architecture of a VLIW processor is by far more complex than that of a RISC architecture.
Status: Open
- Supervisors: Frank K. Gurkaynak, Michael Gautschi
Prerequisites
- VLSI I
- Interest and good knowledge in Computer Architectures (RISC, VLIW architectures)
- VHDL/System Verilog knowledge
Character
- 25% Theory
- 50% ASIC Design
- 25% EDA tools
Professor
Detailed Task Description
Goals
Practical Details
Results
[[[Category:2016]]
