User contributions
From iis-projects
- 15:10, 8 March 2014 diff hist 0 N File:Leveling Loop for Very-Low-Distortion Oscillator.jpg current
- 15:06, 8 March 2014 diff hist +2,570 N Glitches Reduce Listening Time of Your iPod Created page with "thumb ==Short Description== Even though glitching in digital circuits and the resulting extra power dissipated by glitches (also..."
- 15:00, 8 March 2014 diff hist +1,896 N Wiederverwendung (reuse) ganzer Funktionsblöcke beim VLSI-Entwurf Created page with "thumb ==Short Description== Wirtschaftlichkeitsüberlegungen verlangen nach einer Wiederverwendung ganzer Funktionsblöcke. Die heute gängige Ve..." current
- 15:00, 8 March 2014 diff hist 0 N File:Wiederverwendung.gif current
- 14:58, 8 March 2014 diff hist +1,931 N Praxisgerechte Berechnung von Switching Noise in VLSI-Schaltungen Created page with "thumb ==Short Description== Wie die Erfahrung zeigt, liefert das gängige einfache Modell zur Schätzung von Switching Noise übermässig pessimist..." current
- 14:57, 8 March 2014 diff hist 0 N File:Praxisgerechte.gif current
- 14:27, 8 March 2014 diff hist +2,296 N Category:Nano-TCAD Created page with "===Nano-Device Physics (Prof. A. Schenk)=== Research in the Nano-Device Physics Group is concerned with nanoelectronic devices and technologies, first-principle modeling of c..."
- 14:26, 8 March 2014 diff hist +882 N Category:Nano Electronics Created page with "===Description=== The Laboratory for Nanoelectronics investigates the potential of nanoscale materials in electronic devices at each point in the energy life-cycle – collect..."
- 11:45, 7 March 2014 diff hist +5 Category:IcySoC
- 11:44, 7 March 2014 diff hist +4,065 N Category:IcySoC Created page with "<H1>Inexact sub-near-threshold systems for ultra-low power devices</H1> ===Partners=== * [http://tcl.epfl.ch TCL - EPFL] * [http://iclab.epfl.ch ICLAB - EPFL] * [http://csem.c..."
- 11:28, 7 March 2014 diff hist +19 Variability Tolerant Ultra Low Power Cluster
- 10:40, 4 February 2014 diff hist +2,633 N Data Mapping for Unreliable Memories Created page with "File:Data Mapping for Unreliable Memories.png|thumb|480px|Top: Digital communication system employing BPSK transmission over an AWGN channel with unreliable memory. Bottom: ..."
- 10:39, 4 February 2014 diff hist +221 N File:Data Mapping for Unreliable Memories.png Top: Digital communication system employing BPSK transmission over an AWGN channel with unreliable memory. Bottom: Bit-error rate performance of the system assuming convolutional coding for different data representations. current
- 10:33, 4 February 2014 diff hist +2,554 N Exploitation of Inherent Error Resilience of Wireless Systems under Unreliable Silicon Created page with "File:Exploitation of Inherent Error Resilience of Wireless Systems.png|thumb|480px|Top: Simplified block diagram of the considered 3GPP TD-HSPA wireless communication system..."
- 10:33, 4 February 2014 diff hist +220 N File:Exploitation of Inherent Error Resilience of Wireless Systems.png Top: Simplified block diagram of the considered 3GPP TD-HSPA wireless communication system (receive side). Bottom: Throughput performance of the system including re-transmissions with hybrid-ARQ for various defect rates. current
- 10:26, 4 February 2014 diff hist +1 Turbo Decoder Design for High Code Rates →Personnel
- 10:25, 4 February 2014 diff hist +1 Evolved EDGE Physical Layer Incremental Redundancy Architecture →Personnel
- 10:25, 4 February 2014 diff hist +2,149 N High Throughput Turbo Decoder Design Created page with "File:High Throughput Turbo Decoder Design.png|thumb|420px|Chip micrograph of the LTE-Advanced turbo decoder. The overlay depicts the exact locations of the 16 parallel SISO ..."
- 10:24, 4 February 2014 diff hist +161 N File:High Throughput Turbo Decoder Design.png Chip micrograph of the LTE-Advanced turbo decoder. The overlay depicts the exact locations of the 16 parallel SISO decoders used to achieve the 1Gbps throughput. current
- 10:23, 4 February 2014 diff hist +1 Channel Decoding for TD-HSPA
- 10:18, 4 February 2014 diff hist +2,317 N Turbo Decoder Design for High Code Rates Created page with "File:Turbo Decoder Design for High Code Rates.png|thumb|560px|The impact of code rate on throughput and memory capacity of traditional acquisition-run-based turbo decoders (..."
- 10:18, 4 February 2014 diff hist +187 N File:Turbo Decoder Design for High Code Rates.png The impact of code rate on throughput and memory capacity of traditional acquisition-run-based turbo decoders (ATD) and state-metric-propagation-based turbo decoder implementations (STD). current
- 10:12, 4 February 2014 diff hist +2,255 N Channel Decoding for TD-HSPA Created page with "File:Channel Decoding for TD-HSPA.png|thumb|560px|Top: High-level architecture of the channel decoding chain for the downlink terminal side of 3GPP TD-HSPA. Bottom: Layout ..."
- 10:10, 4 February 2014 diff hist +214 N File:Channel Decoding for TD-HSPA.png Top: High-level architecture of the channel decoding chain for the downlink terminal side of 3GPP TD-HSPA. Bottom: Layout of the fabricated turbo and Viterbi decoder prototypes integrated in 180 nm CMOS technology. current
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- 21:54, 3 February 2014 diff hist -166 MediaWiki:Sitenotice Replaced content with "-" current
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