User contributions
From iis-projects
- 11:20, 5 September 2023 diff hist +62 A reduction-capable AXI XBAR for fast M-to-1 communication (1M) →Detailed task description
- 17:18, 4 September 2023 diff hist -19 Accelerating Matrix Multiplication on a 216-core MPSoC (1M) →References
- 17:18, 4 September 2023 diff hist +5,919 N Accelerating Matrix Multiplication on a 216-core MPSoC (1M) Created page with "<!-- Accelerating Matrix Multiplication on a 216-core MPSoC (1M) --> Category:Digital Category:High Performance SoCs Category:2023 Category:Master Thesis Ca..."
- 16:24, 4 September 2023 diff hist +1 Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S) →Status: Available
- 16:24, 4 September 2023 diff hist +11 Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
- 00:03, 10 August 2023 diff hist +6,677 N A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S) Created page with "<!-- A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S) --> Category:Digital Category:High Performance SoCs Category:2023 Category:Maste..."
- 00:03, 10 August 2023 diff hist +51 N File:Snitch block diagram.png A block diagram of the Snitch cluster architecture. current
- 15:53, 9 August 2023 diff hist +1 High Performance SoCs →Matteo Perotti
- 15:53, 9 August 2023 diff hist 0 High Performance SoCs →Luca Colagrande
- 15:52, 9 August 2023 diff hist 0 Matteo Perotti →Contact Information current
- 15:52, 9 August 2023 diff hist 0 User:Colluca →Contact
- 15:19, 12 May 2023 diff hist +12 A reduction-capable AXI XBAR for fast M-to-1 communication (1M) →Detailed task description
- 15:18, 12 May 2023 diff hist +53 A reduction-capable AXI XBAR for fast M-to-1 communication (1M) →Detailed task description
- 15:10, 12 May 2023 diff hist +2 A reduction-capable AXI XBAR for fast M-to-1 communication (1M)
- 15:09, 12 May 2023 diff hist -2 A reduction-capable AXI XBAR for fast M-to-1 communication (1M) →Status: Available
- 15:09, 12 May 2023 diff hist +7 A reduction-capable AXI XBAR for fast M-to-1 communication (1M) →References
- 15:07, 12 May 2023 diff hist +32 A reduction-capable AXI XBAR for fast M-to-1 communication (1M) →Stretch goals
- 15:06, 12 May 2023 diff hist 0 A reduction-capable AXI XBAR for fast M-to-1 communication (1M) →Stretch goals
- 15:06, 12 May 2023 diff hist -13 A reduction-capable AXI XBAR for fast M-to-1 communication (1M) →Stretch goals
- 15:05, 12 May 2023 diff hist +36 A reduction-capable AXI XBAR for fast M-to-1 communication (1M) →Detailed task description
- 15:03, 12 May 2023 diff hist +1 A reduction-capable AXI XBAR for fast M-to-1 communication (1M)
- 15:01, 12 May 2023 diff hist 0 N File:Occamy block diagram.png current
- 15:01, 12 May 2023 diff hist +98 A reduction-capable AXI XBAR for fast M-to-1 communication (1M)
- 14:53, 12 May 2023 diff hist -1,663 A reduction-capable AXI XBAR for fast M-to-1 communication (1M)
- 14:53, 12 May 2023 diff hist -84 A reduction-capable AXI XBAR for fast M-to-1 communication (1M) →Project description
- 14:39, 12 May 2023 diff hist +1,536 A reduction-capable AXI XBAR for fast M-to-1 communication (1M)
- 11:03, 12 May 2023 diff hist +1,667 A reduction-capable AXI XBAR for fast M-to-1 communication (1M)
- 10:15, 12 May 2023 diff hist +34 N File:Axi xbar.png A block diagram of our AXI XBAR IP current
- 10:14, 12 May 2023 diff hist +6,257 N A reduction-capable AXI XBAR for fast M-to-1 communication (1M) Created page with "<!-- A reduction-capable AXI XBAR for fast M-to-1 communication (1M) --> Category:Digital Category:High Performance SoCs Category:2023 Category:Master Thesis..."
- 14:56, 11 May 2023 diff hist +101 Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
- 13:19, 20 January 2023 diff hist +99 Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
- 22:29, 19 January 2023 diff hist 0 Accelerating Stencil Workloads on Snitch using ISSRs (1-2S/B) current
- 22:28, 19 January 2023 diff hist 0 Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
- 22:28, 19 January 2023 diff hist 0 GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S)
- 13:03, 13 January 2023 diff hist +95 Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S) →Status: Available
- 15:14, 22 November 2022 diff hist 0 Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
- 15:12, 22 November 2022 diff hist +1,058 Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
- 12:25, 27 October 2022 diff hist +3 High Performance SoCs →Who are we
- 12:24, 27 October 2022 diff hist +218 High Performance SoCs
- 12:09, 26 October 2022 diff hist +4 Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S) →Optional stretch goals
- 12:08, 26 October 2022 diff hist +13 Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S) →Detailed task description
- 14:13, 13 October 2022 diff hist 0 GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S)
- 14:13, 13 October 2022 diff hist 0 N File:Gdb logo.png current
- 14:12, 13 October 2022 diff hist +52 GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S)
- 14:08, 13 October 2022 diff hist -20 User:Colluca →Available Projects
- 14:08, 13 October 2022 diff hist -20 User:Colluca →Completed Projects
- 14:07, 13 October 2022 diff hist -20 User:Colluca →Projects In Progress
- 13:40, 13 October 2022 diff hist +36 GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S)
- 13:33, 13 October 2022 diff hist +5 GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S) →Your learnings
- 13:32, 13 October 2022 diff hist +6 User:Colluca