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• EECIS
  category = In progress category = In progress
  740 bytes (70 words) - 15:18, 25 September 2019
• Hardware Support for IDE in Multicore Environment
  [[File:Hardware support for IDE in multicore.jpg|thumb]] ===Status: In Progress ===
  2 KB (188 words) - 10:58, 27 March 2014
• Fault Tolerance
  ...ors, however they can induce a large overhead or are not always applicable in case data changes. Furthermore, for certain applications (e.g. handling imp ===Projects In Progress===
  2 KB (213 words) - 13:32, 6 October 2023
• Pulse Oximetry Fachpraktikum
  ...of generating and acquiring signals used in 'photoplethysmography' (PPG). In this thesis, the goal is to '''create''' a new Fachpraktikum where students Each improvement step is compared in size and power with the previous version.
  3 KB (358 words) - 15:59, 18 February 2019
• Predictable Execution
  ...on the same chip as the host CPU, sharing a single DRAM. This has benefits in both programability and performance, due to the removal of the need for dat ...l-time guarantees can be provided, enabling the use of these architectures in a real-time setting.
  2 KB (286 words) - 18:48, 10 November 2020
• Creating a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B)
  [[Category:In progress]] == Status: In Progress ==
  2 KB (226 words) - 14:22, 27 February 2024
• Implementation of a Cache Reliability Mechanism (1S/M)
  [[Category:In progress]] == Status: In Progress ==
  2 KB (267 words) - 14:22, 27 February 2024
• Fault-Tolerant Floating-Point Units (M)
  [[Category:In progress]] == Status: In Progress ==
  2 KB (273 words) - 14:23, 27 February 2024
• Reconfigurability of SHA-3 candidates
  In December 2010, the 5 finalists of the SHA-3 competition were announced. The : Interest in Cryptography
  2 KB (300 words) - 14:11, 13 March 2014
• Novel Metastability Mitigation Technique
  ...tching clock. As a result, the circuit persists in an unstable equilibrium in metastability, which influences the correctness of the data and the power c ...against metastability, but it does not ensure the correctness of the data. In this project, the student will explore a novel approach that employs passiv
  2 KB (203 words) - 18:03, 16 December 2022
• Switched-capacitor power amplifier for IoT mobile communications: design of signal processing path
  ...ty will first be investigated at a functional level before implementing it in a CMOS process. ===Status: In Progress ===
  2 KB (356 words) - 15:55, 6 May 2019
• Acceleration and Transprecision
  ...cient. Such accelerators are not limited to high performance sector alone. In low power computing, they allow complex tasks such as computer vision or cr ===Projects In Progress===
  2 KB (275 words) - 17:05, 24 November 2023
• Ultra-low power sampling front-end for acquisition of physiological signals
  ...a switched capacitor circuit before converting it into the digital domain. In this thesis it will be possible to learn the whole the design cycle includi ===Status: In Progress ===
  2 KB (359 words) - 16:06, 6 May 2019
• Ultra-low power transceiver for implantable devices
  ...a 130nm CMOS technology and offers to design radio and base-band circuits. In the thesis it will be possible to learn the whole the design cycle includin ===Status: In Progress ===
  2 KB (347 words) - 11:43, 20 August 2021
• David J. Mack
  ...hard Karls University in Tübingen, Germany. In 2015, he acquired his Ph.D. in Cognitive and Behavioral Neuroscience at the same university. Since 2015 he If you are interested in eye tracking, biological signal processing or even a neuroscience research
  2 KB (310 words) - 17:41, 31 August 2016
• Signal to Noise Ratio Estimation for 3G standards
  ...to-noise ratio (SNR) is the basis for almost any digital signal processing in a receiver. ...semester project you will implement an efficient SNR-estimation algorithm in order to obtain an energy and area-efficient solution. This can be done as
  2 KB (300 words) - 11:23, 14 April 2016
• Analog Layout Engine
  ...rogramming languages to automatically generate parametrized cells (PCELLS) in Cadence. ===Status: In Progress ===
  2 KB (329 words) - 17:44, 21 December 2017
• Successive Approximation Register (SAR) ADC
  ===Status: In Progress === [[Category:In progress]]
  2 KB (319 words) - 17:43, 21 December 2017
• Assessment of novel photovoltaic architectures by circuit simulation
  ...fy some of the simulation results experimentally. An extension of the work in form of a master thesis or lab assistant is possible. : Interest in circuit simulation
  3 KB (355 words) - 12:07, 17 January 2014
• Application Specific Frequency Synthesizers (Analog/Digital PLLs)
  In this project, students will learn the key techniques for an advanced freque : Basic knowledge in analog circuit design
  3 KB (350 words) - 14:52, 25 September 2019

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