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Showing below up to 50 results in range #351 to #400.
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- High Performance Digitally-Assisted Time Domain ADC Design for DPLL used in Cellular IOT (7 revisions)
- SW/HW Predictability and Security (7 revisions)
- An all Standard-Cell Based Energy Efficient HW Accelerator for DSP and Deep Learning Applications (7 revisions)
- EEG artifact detection for epilepsy monitoring (7 revisions)
- Charging System for Implantable Electronics (7 revisions)
- Physical Layer Implementation of HSPA+ 4G Mobile Transceiver (7 revisions)
- Optimizing the Pipeline in our Floating Point Architectures (1S) (7 revisions)
- A Flexible FPGA-Based Peripheral Platform Extending Linux-Capable Systems on Chip (1-3S/B) (7 revisions)
- FFT HDL Code Generator for Multi-Antenna mmWave Communication (7 revisions)
- Development of statistics and contention monitoring unit for PULP (7 revisions)
- RVfplib (7 revisions)
- Creating a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B) (7 revisions)
- Zephyr RTOS on PULP (7 revisions)
- System Analysis and VLSI Design of NB-IoT Baseband Processing (7 revisions)
- Characterization techniques for silicon photonics-Lumiphase (7 revisions)
- Bateryless Heart Rate Monitoring (7 revisions)
- Autonomous Sensing For Trains In The IoT Era (7 revisions)
- Mauro Salomon (7 revisions)
- Battery indifferent wearable Ultrasound (7 revisions)
- Ultrasound Low power WiFi with IMX7 (7 revisions)
- Make Cellular Internet of Things Receivers Smart (7 revisions)
- Streaming Integer Extensions for Snitch (M/1-2S) (7 revisions)
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core (7 revisions)
- Efficient Search Design for Hyperdimensional Computing (7 revisions)
- Contrastive Learning for Self-supervised Clustering of iEEG Data for Epileptic Patients (7 revisions)
- Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Training Strategy And Algorithmic optimizations (7 revisions)
- A RISC-V ISA Extension for Scalar Chaining in Snitch (M) (7 revisions)
- Extending the HERO RISC-V HPC stack to support multiple devices on heterogeneous SoCs (M/1-3S) (7 revisions)
- Development of a Rockfall Sensor Node (7 revisions)
- Optimal routing for 2D Mesh-based Analog Compute-In-Memory Accelerator Architecture (IBM-Zurich) (6 revisions)
- A Recurrent Neural Network Speech Recognition Chip (6 revisions)
- Design of a Low Power Smart Sensing Multi-modal Vision Platform (6 revisions)
- Creating a HDMI Video Interface for PULP (6 revisions)
- VLSI Implementation of a 5G Ciphering Accelerator (6 revisions)
- FPGA-based Testbed Implementation of an Extended-Coverage Point-to-Point Communication Link for the Internet of Things (6 revisions)
- Exploring NAS spaces with C-BRED (6 revisions)
- Android Software Design (6 revisions)
- Low-power Temperature-insensitive Timer (6 revisions)
- Improved Collision Avoidance for Nano-drones (6 revisions)
- Bluetooth Low Energy receiver in 65nm CMOS (6 revisions)
- Graph neural networks for epileptic seizure detection (6 revisions)
- Advanced Physical Design: Reinforcement Learning for Macro Placement and Mix-Placer (B/1-2S) (6 revisions)
- Multiuser Equalization and Detection for 3GPP TD-SCDMA (6 revisions)
- Towards Self Sustainable UAVs (6 revisions)
- Compression of iEEG Data (6 revisions)
- PULPonFPGA: Lightweight Virtual Memory Support - Software Cache (6 revisions)
- Ultrasound image data recycler (6 revisions)
- Pretraining Foundational Models for EEG Signal Analysis Using Open Source Large Scale Datasets (6 revisions)
- Benchmarking a RISC-V-based Server on LLMs/Foundation Models (SA or MA) (6 revisions)
- Efficient Synchronization of Manycore Systems (M/1S) (6 revisions)
