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• ML based Quantitative Movement Analysis on a Portable IoT Camera (1-2S/B)
  ...ead to injuries. In clinical biomechanics, understanding changes in muscle and tendon properties is vital for creating effective treatment plans. ...particularly during fast movements like running, due to high acceleration and perspiration (falling off sensors), or when working with specific patient g
  6 KB (735 words) - 12:12, 23 July 2023
• Floating-Point Divide & Square Root Unit for Transprecision
  ...ly. In contrast to approximate computing where the precision of the entire system is reduced - often incurring loss in result quality - transprecision comput ...eresting for classic video and audio processing, but also machine learning and scientific computing workloads.
  8 KB (1,135 words) - 17:09, 29 July 2020
• Heroino: Design of the next CORE-V Microcontroller
  ...RE-V CV32E4 and CVA6 microprocessors, previously known as RI5CY and Ariane and originally developed at ETH Zurich. ...perience easy and standard, with industrial standard peripherals subsystem and software (as freeRTOS).
  9 KB (1,314 words) - 00:01, 7 February 2021
• PULP in space - Fault Tolerant PULP System for Critical Space Applications
  ...ircuits after their fabrication, such technique would incur into low yield and high costs if applied to modern processes. ...pikes due to cosmic rays being captured by sequential elements, taking the system into a faulty state.
  6 KB (980 words) - 14:46, 2 June 2021
• Manycore System on FPGA (M/S/G)
  <!-- Manycore System on FPGA --> [[Category:Computer Architecture]]
  8 KB (1,319 words) - 10:41, 6 July 2021
• Hardware Acceleration
  ...nce sector alone. In low power computing, they allow complex tasks such as computer vision or cryptography to be performed under a very tight power budget. Wit ...world performance as communication and data exchange between the processor and accelerator become major bottlenecks.
  7 KB (917 words) - 17:04, 24 November 2023
• Signal Acquisition and Clock Offset Compensation for High-Rate Pulse UWB PHYs
  ...w power, low cost, provably secure, high link budget (communication range) and automotive qualified wireless ranging device simply powered from a small co ...and carrier recovery approaches for signal acquisition of HRP UWB signals and clock offset compensation/tracking techniques for payload data decoding. Th
  5 KB (584 words) - 12:09, 29 October 2020
• Semi-Custom Digital VLSI for Processing-in-Memory
  ...o hit a “memory wall,” where most of the computations’ time, energy, and bandwidth is consumed by memory operations. This problem is further aggrava ...test, or migrate to other technology nodes, due to their analog component, and/or (ii) not applicable today, due to the use of immature semiconductor tech
  7 KB (882 words) - 14:33, 28 July 2021
• ASIC Implementation of Jammer Mitigation
  ...t research topic in wireless communication. Many different linear [1], [2] and non-linear (e.g., deep learning based [3]) jammer mitigation algorithms hav ...fficient VLSI implementation. The student will then synthesize this design and tape out a chip using CMOS technology.
  5 KB (662 words) - 13:31, 10 May 2023
• An all Standard-Cell Based Energy Efficient HW Accelerator for DSP and Deep Learning Applications
  ...way to store volatile data, their potential for agressive voltage scaling and thus increasing the systems energy efficiency is limited. The goal of this [[File:Pulpissimo_archi.png|thumb|800px|PULPissimo SoC Architecture]]
  7 KB (1,032 words) - 15:31, 16 November 2020
• Implementation of a Heterogeneous System for Image Processing on an FPGA (S)
  ...e, due to their host processor capabilities, while having high performance and energy efficiency through their PMCAs. It's aim is to separate the function applied to the image (pipeline), and the sequence in which the algorithm is executed (schedule).
  5 KB (737 words) - 17:26, 2 November 2020
• A Flexible Peripheral System for High-Performance Systems on Chip (M)
  <!-- (M): A Flexible Peripheral System for High-Performance Systems on Chip --> * VLSI I and II or equivalent: Understanding of at least one RTL language and ASIC design principles.
  11 KB (1,675 words) - 15:40, 15 March 2021
• A Snitch-based Compute Accelerator for HERO (M/1-2S)
  * VLSI I or equivalent: Understanding of at least one RTL language and FPGA design principles. * Basic prior knowledge of embedded / bare-metal C and Assembly
  11 KB (1,617 words) - 23:59, 6 February 2021
• Peak-to-average power Reduction
  ...he tools to be learned in this project are numerical (convex) optimization and deep unfolding, a recent paradigm to tune algorithm parameters using deep l [[Category:Computer Architecture]]
  4 KB (513 words) - 14:16, 24 November 2021
• Software-Defined Paging in the Snitch Cluster (2-3S)
  [[Category:Computer Architecture]] ...le-precision FPUs and utilization-boosting extensions to maximize the area and energy spent on useful computation.
  4 KB (563 words) - 20:08, 15 February 2021
• DaCe on Snitch (M/1-3S)
  #Redirect [[LLVM and DaCe for Snitch (1-2S)]] [[Category:Computer Architecture]]
  2 KB (333 words) - 20:05, 15 February 2021
• Coherence-Capable Write-Back L1 Data Cache for Ariane (M)
  [[Category:Computer Architecture]] ...[1]. It is capable of booting Linux and it is widely used both in academia and industry. Ariane features a write-back level 1 data cache, which temporally
  3 KB (395 words) - 16:32, 15 November 2022
• IP-Based SoC Generation and Configuration (1-3S/B)
  [[Category:Computer Architecture]] ...evaluate their impact. Moving to more complex SoCs, top-level connectivity and parameterization become a major design issue:
  4 KB (617 words) - 10:19, 3 November 2023
• Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S)
  ...s private memory banks---this, however, impacts the programmability of the system. ...eved through a cache hierarchy, which impacts the energy efficiency of the system through its non-negligible power consumption.
  8 KB (1,196 words) - 10:41, 6 July 2021
• Self-Supervised User Positioning in Cell-Free Massive MIMO Systems
  ...(DM-MIMO) systems are channel charting [3], fingerprinting techniques [1], and triangulation/trilateration [4]. ...as the potential to significantly increase localization accuracy in indoor and rural scenarios, while avoiding the need of labeled training data.
  8 KB (931 words) - 17:27, 23 November 2021

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