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• Design and Implementation of Digital Spiking Neurons for Ultra-Low-Power In-Cluster Coprocessors
  Current interest in brain-inspired and neuromorphic computer architectures is enormous, due to ...u will integrate the complete accelerator inside the PULP platform (either in the simulation platform or the FPGA emulation platform).
  5 KB (784 words) - 14:50, 30 November 2016
• High-Throughput Hardware Implementations of Authenticated Encryption Algorithms
  These days, security breaches are omnipresent in our daily news thanks to the NSA and others. Therefore, new cryptographic a ...ikipedia.org/wiki/Advanced_Encryption_Standard AES]. If you are interested in working on hardware implementations of state-of-the-art security algorithms
  2 KB (317 words) - 13:13, 14 April 2016
• Android Software Design
  ...th improved display, signal processing for, e.g., heart-beat rate read-out in an ECG is desirable. The software should further include a GUI for the conf ===Status: In Progress ===
  2 KB (278 words) - 16:57, 12 July 2022
• Investigation of the source starvation effect in III-V MOSFET
  ...ion model capable of capturing the distribution of the electron population in the source contact of III-V MOSFETs and of determining whether or not sourc : Interest in device modeling
  3 KB (331 words) - 15:40, 4 September 2019
• Full-band simulations of InP/GaAsSb/InP Double Heterojunction Bipolar Transistors (DHBTs)
  ...mulator what happens if the GaAsSb/InP junction contains atomic roughness. In this case, momentum conservation is broken and L-valley electrons might eve : Interest in device modeling
  3 KB (377 words) - 15:44, 4 September 2019
• Design study of tunneling transistors based on a core/shell nanowire structures
  ...could provide better performance than standard ones. The key idea consists in using a core/shell nanowire structure where the core and the shell have dif : Interest in device modeling
  3 KB (357 words) - 15:38, 4 September 2019
• Computation of Phonon Bandstructure in III-V Nanostructures
  [[File:Computation of Phonon Bandstructure in III-V Nanostructures.png|280px|thumb]] ...ld's summation method in bulk structures, it is not clear how to handle it in nanostructures without too much increasing the computational burden.
  3 KB (363 words) - 15:37, 4 September 2019
• Simulation of Negative Capacitance Ferroelectric Transistor
  ...ring ON-OFF switching processes. In FETs, the major difficulty to overcome in order to minimize their power consumption is the value of their inverse sub ===Status: In Progress ===
  3 KB (449 words) - 15:37, 4 September 2019
• Investigation of Redox Processes in CBRAM
  ...a large number of different metal/oxide pairs so that their applicability in CBRAM applications can be validated. ...developed an electrochemical model in COMSOL to simulate ON/OFF switching in CBRAM. So far, the model still depends on a number of free input parameters
  4 KB (488 words) - 17:12, 16 September 2021
• Investigation of Metal Diffusion in Oxides for CBRAM Applications
  ...umber of metal/oxide pairs and analyze them regarding their applicability in CBRAM applications ...group has developed a model in COMSOL to simulate ON/OFF switching in CBRAM. So far, the model depends on a number of free input parameters, amon
  3 KB (448 words) - 17:11, 16 September 2021
• Development of an efficient algorithm for quantum transport codes
  :Good knowledge in solid state physics and quantum mechanics ===Status: In Progress ===
  2 KB (284 words) - 17:10, 16 September 2021
• Integrated silicon photonic structures
  physical effect available in integrated photonics circuits has been a scientific and internship project is placed in the heart of our R&D activities and covers topics related
  4 KB (608 words) - 13:58, 23 June 2021
• Analysis and Design of Power Efficient RF/ mm-Wave LC-tank Oscillator in 28nm for 5G communication applications
  ...ch means the high purity frequency carriers are required to be synthesized in the range from 15 GHz to even 60 GHz. ...lution (PLL), VCO is the key part of the whole frequency solution since it in general consumes 70% to even 80% of the full power budget of a PLL as well
  4 KB (518 words) - 16:07, 6 May 2019
• A Unified-Multiplier Based Hardware Architecture for Elliptic Curve Cryptography
  In addition to the "pseudo-processor-controlled approach", the [[Category:In progress]]
  2 KB (326 words) - 12:26, 26 March 2015
• Hardware Support for IDE in Multicore Environment
  [[File:Hardware support for IDE in multicore.jpg|thumb]] ===Status: In Progress ===
  2 KB (188 words) - 10:58, 27 March 2014
• FPGA-Based Digital Frontend for 3G Receivers
  ...n receiver for 3G mobile communications standard, such as the ones present in any mobile phone, consist of many digital blocks which process the received ...s in the receiver, such as a DC-offset, have to be corrected. This is done in the Digital Frontend (DFE).
  2 KB (348 words) - 20:01, 26 September 2017
• ASIC
  In an ASIC (Application Specific Integrated Circuit) project you will be worki ...nding on the project, your design may be sent for manufacturing to be used in future projects.
  1 KB (165 words) - 19:52, 10 February 2015
• FPGA
  ...prototypes and/or testbeds used to simulate the behavior of large systems. In such a project you will ==Projects in Progress==
  1,020 bytes (132 words) - 19:50, 10 February 2015
• Indoor Positioning with Bluetooth
  : Interest in wireless communications : Knowledge in Matlab, C and/or VHDL is of advantage
  3 KB (449 words) - 12:12, 4 November 2019
• Advanced 5G Repetition Combining
  ...s to a brute-force approach to combining this information. As a first step in your project, you will study ways to reduce the complexity on an algorithmi ===Status: In Progress ===
  3 KB (345 words) - 10:52, 5 April 2022

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