ASIC
From iis-projects
In an ASIC (Application Specific Integrated Circuit) project you will be working on the design of an integrated circuit. This will include:
- Researching different architectures to find the most suitable one for the project
- Designing the system architecture
- Defining the circuit using hardware description languages (HDL) such as (System Verilog or VHDL) for digital projects, and schematic entry for analog projects.
- Running simulations to verify the correct functionality and ensuring that the specifications of the circuit are met
- The actual physical design of the integrated circuit
- Verifications to make sure that the circuit can be properly manufactured
- Providing documentation for the test and use of the integrated circuit
Depending on the project, your design may be sent for manufacturing to be used in future projects.
Available Projects
- RISC-V based Implementation of Secure Ranging According to IEEE 802.15.4z UWB
- Spiking Neural Network for Autonomous Navigation
- Event-Driven Convolutional Neural Network Modular Accelerator
- Level Crossing ADC For a Many Channels Neural Recording Interface
- Scalable Heterogeneous L1 Memory Interconnect for Smart Accelerator Coupling in Ultra-Low Power Multicores
- Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core
- Resilient Brain-Inspired Hyperdimensional Computing Architectures
- Variable Bit Precision Logic for Deep Learning and Artificial Intelligence
- Single-Bit-Synapse Spiking Neural System-on-Chip
Projects in Progress
- Physical Implementation of ITA (2S)
- 3D Matrix Multiplication Unit for ITA (1S)
- Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B)
- Channel Estimation for 5G Cellular IoT and Fast Fading Channels
- An all Standard-Cell Based Energy Efficient HW Accelerator for DSP and Deep Learning Applications
Completed Projects
- Spatz grows wings: Physical Implementation of a Vector-Powered Manycore System (2S)
- Design and Implementation of a Fully-digital Platform-independent Integrated Temperature Sensor Enabling DVFS in Open-source Tapeouts (1-3S/B)
- MCU Bus and Memory Generator: implementation of a Highly Configurable bus and memory subsystem for a RISC-V based microcontroller.
- Advanced 5G Repetition Combining
- Physical Implementation of Ara, PULP's Vector Machine (1-2S)
- An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)
- Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S)
- A Flexible Peripheral System for High-Performance Systems on Chip (M)
- NVDLA meets PULP
- Hardware Accelerators for Lossless Quantized Deep Neural Networks
- Energy-Efficient Brain-Inspired Hyperdimensional Computing
- Floating-Point Divide & Square Root Unit for Transprecision
- Timing Channel Mitigations for RISC-V Cores
- Indoor Positioning with Bluetooth
- Deep Learning for Brain-Computer Interface
- Trace Debugger for custom RISC-V Core
- Low-Energy Cluster-Coupled Vector Coprocessor for Special-Purpose PULP Acceleration
- Shared Correlation Accelerator for an RF SoC
- IoT Turbo Decoder
- Creating a HDMI Video Interface for PULP
- Standard Cell Compatible Memory Array Design
- VLSI Implementation of a Low-Complexity Channel Shortener for 2G EC-GSM-IoT and Evolved EDGE
- Accelerator for Spatio-Temporal Video Filtering
- Design and Implementation of Digital Spiking Neurons for Ultra-Low-Power In-Cluster Coprocessors
- 3D Turbo Decoder ASIC Realization
- High-Throughput Hardware Implementations of Authenticated Encryption Algorithms
- ASIC Implementation of High-Throughput Next Generation Turbo Decoders
- Spatio-Temporal Video Filtering
- An FPGA-Based Testbed for 3G Mobile Communications Receivers
- Baseband Meets CPU
- Vector Processor for In-Memory Computing
- StoneEDGE: An EC-GSM-IoT and Evolved EDGE PHY ASIC
- RazorEDGE: An Evolved EDGE DBB ASIC
- Design and VLSI Implementation of a Constrained-Viterbi Algorithm Equalizer for 3GPP TD-HSPA
- Design and Implementation of an Approximate Floating Point Unit
- A Unified-Multiplier Based Hardware Architecture for Elliptic Curve Cryptography
- Putting Together What Fits Together - GrÆStl