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  • ...n receiver for 3G mobile communications standard, such as the ones present in any mobile phone, consist of many digital blocks which process the received ...s in the receiver, such as a DC-offset, have to be corrected. This is done in the Digital Frontend (DFE).
    2 KB (348 words) - 20:01, 26 September 2017
  • ...th improved display, signal processing for, e.g., heart-beat rate read-out in an ECG is desirable. The software should further include a GUI for the conf ===Status: In Progress ===
    2 KB (278 words) - 16:57, 12 July 2022
  • ...[https://www.infineon.com/cms/austria/en/ Infineon Technologies] (Austria, in 2014-​​​2015). During his PhD, he worked on [https://air.uniud.it/ret '''Most of the projects evolve very fast. If you are interested in the research areas mentioned above, send me a message to discuss up-to-date
    3 KB (406 words) - 17:17, 3 May 2024
  • ...a ConvNet for a different encoding has been done several times before, but in order to optimize for best compression we need to quantize intermediate res In this project you learn the basics of ConvNets, develop such a quantization
    3 KB (362 words) - 16:25, 30 October 2020
  • ...orth to run expensive computations or whether there is not enough activity in the environment. This approach is called event-driven computing. ===Projects In Progress===
    2 KB (266 words) - 11:16, 5 November 2020
  • ...face exposed to molecules, as shown above, allows to explore its potential in gas sensor applications. To study the influence of certain reactive molecu • Strong interest in semiconductor device physics and simulation
    2 KB (302 words) - 18:47, 10 November 2022
  • ...research results and to achieve a comparable efficiency as the best design in the figure. ===Status: In Progress ===
    2 KB (368 words) - 18:58, 19 December 2016
  • ...ated comparators with similar delay time (determined by the clock period). In this thesis different topologies will be compared to each other for resolut ===Status: In Progress ===
    3 KB (362 words) - 17:35, 21 December 2017
  • ...plementation. After the back-end design, the final ASIC will be fabricated in high-end CMOS technology. ===Status: In Progress ===
    3 KB (392 words) - 12:33, 15 April 2016
  • ...ll be investigated first at behavioral level, followed by a circuit design in 130nm CMOS. It will be possible to learn the whole the design cycle includi ===Status: In Progress ===
    3 KB (358 words) - 11:40, 20 August 2021
  • :Good knowledge in solid state physics and quantum mechanics ===Status: In Progress ===
    2 KB (284 words) - 17:10, 16 September 2021
  • ...rove the performance of this parallel bank of ADCs both in the digital and in the analog domain. : Interest in mobile communications
    3 KB (405 words) - 16:13, 29 December 2016
  • [[Category:In progress]] == Status: In Progress ==
    3 KB (395 words) - 16:32, 15 November 2022
  • ...mator and equalizer for LTE Advanced. You will compare existing algorithms in MATLAB and come up with an efficient solution suitable for hardware impleme ...rform the back-end design such that the resulting chip can be manufactured in high-end CMOS technology. During this thesis you will get an insight into t
    3 KB (385 words) - 11:13, 14 April 2016
  • In this project, we have developed several ConvNets to remove compression arti ===Status: {Available, Reserved, In Progress, Completed}===
    2 KB (285 words) - 18:16, 29 August 2016
  • ...e capacity of batteries is becoming a critical issue in our modern society in order to fully exploit the potential of renewable energies such as wind or : Interest in Device Modelling
    3 KB (362 words) - 15:43, 4 September 2019
  • ...are around and which synchronization codes are used. Solving this problem in dedicated hardware will be the topic of this thesis. Synchronization in time will detect the position of the frame boundaries and reveal the Cell I
    3 KB (420 words) - 11:22, 14 April 2016
  • ...us-time converter for up to 10kHz bandwidth with 80dB SNR will be designed in 130nm CMOS. It will be possible to learn the whole the design cycle includi ===Status: In Progress ===
    3 KB (375 words) - 17:46, 2 May 2017
  • [[Category:In progress]] == Status: In progress ==
    3 KB (342 words) - 13:02, 12 February 2024
  • ...rical engineering and information technology from ETH Zürich, Switzerland, in 2011. Since then he is pursuing There are several projects currently available, which are listed in this section. Most of them can be adapted to a Masters or a Semester thesis
    2 KB (336 words) - 17:27, 1 November 2017

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