...spective users can develop their programs, and transfer them to the RISC-V processor, as well as establish connections to basic peripherals. It is planned to ma
[[Category:Processor]]
4 KB (497 words) - 16:50, 21 June 2018
...it should not have any impact on the maximum achievable clock speed of the processor. Another challenge in designing a trace debugger is the fact that on-chip R
* Basic knowledge of computer architecture/processor design as thought in the Energy-Efficient Parallel Computing Systems for Da
5 KB (729 words) - 11:27, 11 December 2018
...e the backbone of big data and scientific computing. While general-purpose processor architectures such as Intel's x86 provide good performance across a wide va
...and real-world performance as communication and data exchange between the processor and accelerator become major bottlenecks.
7 KB (917 words) - 17:04, 24 November 2023
...ract additional data. The idea is to use the very efficient GAP9 multicore processor and deploy multi-modal neural networks to perform feature extraction, predi
...[https://greenwaves-technologies.com/gap9_processor/ GAP9 IoT Application Processor]
4 KB (531 words) - 17:09, 16 May 2024
...ract additional data. The idea is to use the very efficient GAP9 multicore processor and deploy multi-modal neural networks to perform feature extraction, predi
...[https://greenwaves-technologies.com/gap9_processor/ GAP9 IoT Application Processor]
4 KB (534 words) - 17:09, 16 May 2024
* compares against Ara, a vector processor based on the RISC-V Vector extension
...8] Zaruba, Florian "Ariane: An open-source 64-bit RISC-V Application-Class Processor and latest Improvements" [https://content.riscv.org/wp-content/uploads/2018
6 KB (799 words) - 13:42, 10 November 2020
This project aims to extend the I/O peripherals of a Linux-capable RISC-V SoC processor with a novel designed CAN interface.
This project aims to extend the I/O peripherals of a Linux-capable RISC-V SoC processor with a novel designed CAN interface.
4 KB (554 words) - 09:28, 3 November 2023
:[1] [http://arxiv.org/abs/1404.3162 A Signal Processor for Gaussian Message Passing]
2 KB (236 words) - 09:46, 12 October 2017
[[Category:Processor]]
2 KB (240 words) - 16:57, 12 July 2022
...ftware co-design in which part of the algorithm will be mapped onto a PULP processor while computational complex tasks are realized in dedicated hardware accele
[[Category:Processor]]
4 KB (555 words) - 16:36, 23 May 2018
...sy reconfigurability of the oscillator with an external microcontroller or processor, while having outputs based on the I2S protocol that directly connect with
[[Category:Processor]]
5 KB (621 words) - 18:09, 9 October 2022
...le Modular Redundancy (TMR), to ensure a reliability level. For example, a processor core is replicated an odd number of times, and a voting mechanism is used t
...be used in combination with the [https://www.github.com/lowRISC/ibex Ibex] processor core. Similar to RI5CY, Ibex implements the RV32IMC instruction set archite
6 KB (980 words) - 14:46, 2 June 2021
...ovement, by featuring a comparably large register file. On an out-of-order processor we could execute the original version of the program and still expect the p
...Snitch core developed in our group. Snitch is a pseudo dual-issue in-order processor, targeting energy-efficient floating-point computations. Snitch-based accel
7 KB (1,153 words) - 18:58, 21 April 2024
...complex enough and frankly just boring whereas fully-developed IPs, like a processor core, consists of tens to hundreds of thousands gates. Even our smallest co
2 KB (248 words) - 20:02, 15 February 2021
...ing the design before it can be delivered for tapeout. For general purpose processor designs, verifying the functionality involves running some code on the core
If your processor has a debugging interface (exposed e.g. over JTAG) and can be implemented o
8 KB (1,186 words) - 11:49, 13 March 2024
PPAC (Parallel Processor in Associative Content-Addressable Memory) [1] is a hardware accelerator th
...benchmarking, the student will also integrate PPAC together with a RISC-V processor.
7 KB (804 words) - 19:45, 21 November 2021
...So far our DMA engine works on physical memory only, requiring either the processor to do the PM/VM translation or relying on an external IOMMU (IO Memory Mana
2 KB (249 words) - 09:36, 3 November 2023
[[File:lteTestbed.jpg|thumb|Figure 2: LTE testbed with digital baseband and processor on an FPGA and RF-IC on the [[evaLTE]] FMC module.]]
2 KB (245 words) - 10:39, 6 November 2017
...e the backbone of big data and scientific computing. While general purpose processor architectures such as Intel's x86 provide good performance across a wide va
2 KB (275 words) - 17:05, 24 November 2023
The goal of the mini-project is to explore a processor i.MX 7ULP from NXP) for low-power ultrasound data streaming through WiFi.
2 KB (240 words) - 16:56, 16 September 2022
