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Showing below up to 50 results in range #751 to #800.

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  1. Vector-based Parallel Programming Optimization of Communication Algorithm (1-2S/B)‏‎ (11:57, 31 October 2023)
  2. Routing 1000s of wires in Network-on-Chips (1-2S/M)‏‎ (16:23, 31 October 2023)
  3. Energy Efficient SoCs‏‎ (15:59, 1 November 2023)
  4. Runtime partitioning of L1 memory in Mempool (M)‏‎ (10:38, 2 November 2023)
  5. Enabling Efficient Systolic Execution on MemPool (M)‏‎ (10:39, 2 November 2023)
  6. On-Device Training Sparse Sub-Tensor Update Scheme Optimization for CNN-based tasks (SA or MA)‏‎ (13:29, 2 November 2023)
  7. Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B)‏‎ (09:27, 3 November 2023)
  8. Fitting Power Consumption of an IP-based HLS Approach to Real Hardware (1-3S)‏‎ (09:27, 3 November 2023)
  9. Design of an Energy-Efficient Ethernet Interface for Linux-capable Systems‏‎ (09:28, 3 November 2023)
  10. Design of a CAN Interface to Enable Reliable Sensors-to-Processors Communication for Automotive-oriented Embedded Applications (1M)‏‎ (09:28, 3 November 2023)
  11. Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1M)‏‎ (09:30, 3 November 2023)
  12. Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (B/1-3S)‏‎ (09:34, 3 November 2023)
  13. Extension and Evaluation of TinyDMA (1-2S/B/2-3G)‏‎ (09:35, 3 November 2023)
  14. Finalizing and Releasing Our Open-source AXI4 IPs (1-3S/B/2-3G)‏‎ (09:36, 3 November 2023)
  15. Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B)‏‎ (09:36, 3 November 2023)
  16. Enhancing Our DMA Engine With Virtual Memory (M/1-3S/B)‏‎ (09:36, 3 November 2023)
  17. Towards a High-performance Open-source Verification Suite for AXI-based Systems (M/1-3S/B)‏‎ (09:38, 3 November 2023)
  18. Improving SystemVerilog Support for Free And Open-Source EDA Tools (1-3S/B)‏‎ (09:38, 3 November 2023)
  19. Modeling High Bandwidth Memory for Rapid Design Space Exploration (1-3S/B)‏‎ (09:39, 3 November 2023)
  20. Creating A Boundry Scan Generator (1-3S/B/2-3G)‏‎ (09:55, 3 November 2023)
  21. IP-Based SoC Generation and Configuration (1-3S/B)‏‎ (10:19, 3 November 2023)
  22. Towards Formal Verification of the iDMA Engine (1-3S/B)‏‎ (10:21, 3 November 2023)
  23. Evaluating The Use of Snitch In The PsPIN RISC-V In-network Accelerator (M)‏‎ (10:24, 3 November 2023)
  24. Creating A Reshuffling Mid-end For Reorganizing Data Inside The Compute Cluster (1-3S/B)‏‎ (10:25, 3 November 2023)
  25. Creating an At-memory Low-overhead Bufferless Matrix Transposition Accelerator (1-3S/B)‏‎ (10:27, 3 November 2023)
  26. Advanced Physical Design: Reinforcement Learning for Macro Placement and Mix-Placer (B/1-2S)‏‎ (10:50, 3 November 2023)
  27. Scaleout Study on Interleaved Memory Transfers in Huge Manycore Systems with Multiple HBM Channels (M/1-3S)‏‎ (11:18, 3 November 2023)
  28. Big Data Analytics Benchmarks for Ara‏‎ (11:34, 3 November 2023)
  29. Efficient Execution of Transformers in RISC-V Vector Machines with Custom HW acceleration (M)‏‎ (11:35, 3 November 2023)
  30. New RVV 1.0 Vector Instructions for Ara‏‎ (11:37, 3 November 2023)
  31. Virtual Memory Ara‏‎ (11:38, 3 November 2023)
  32. Investigating the Cost of Special-Case Handling in Low-Precision Floating-Point Dot Product Units (1S)‏‎ (18:20, 3 November 2023)
  33. Federico Villani‏‎ (18:30, 8 November 2023)
  34. Design of Streaming Data Platform for High-Speed ADC Data‏‎ (11:16, 9 November 2023)
  35. Designing a Fault-Tolerant On-Chip Interconnect (1-2S/M)‏‎ (17:19, 13 November 2023)
  36. Practical Reconfigurable Intelligent Surfaces (RIS)‏‎ (12:25, 16 November 2023)
  37. Advanced Data Movers for Modern Neural Networks‏‎ (16:18, 23 November 2023)
  38. Cycle-Accurate Event-Based Simulation of Snitch Core‏‎ (22:54, 23 November 2023)
  39. Hardware Acceleration‏‎ (17:04, 24 November 2023)
  40. Acceleration and Transprecision‏‎ (17:05, 24 November 2023)
  41. Taping a Safer Silicon Implementation of Snitch (M/2-3S)‏‎ (18:47, 24 November 2023)
  42. Modeling FlooNoC in GVSoC (S/M)‏‎ (15:15, 4 December 2023)
  43. Object Detection and Tracking on the Edge‏‎ (10:55, 5 December 2023)
  44. Design of a Low Power Smart Sensing Multi-modal Vision Platform‏‎ (11:02, 5 December 2023)
  45. Design of a High-​performance Hybrid PTZ for Multimodal Vision Systems‏‎ (11:07, 5 December 2023)
  46. Battery indifferent wearable Ultrasound‏‎ (18:42, 6 December 2023)
  47. Automatic unplugging detection for Ultrasound probes‏‎ (18:42, 6 December 2023)
  48. In-ear EEG signal acquisition‏‎ (19:01, 6 December 2023)
  49. EEG earbud‏‎ (19:01, 6 December 2023)
  50. Advanced EEG glasses‏‎ (19:01, 6 December 2023)

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