Difference between revisions of "Heroino: Design of the next CORE-V Microcontroller"
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| − | + | ==Introduction== | |
The CORE-V MCU serves as a minimal basis to demonstrate the capabilities of the OpenHW Group CORE-V CV32E4 and CVA6 microprocessors, previously known as RI5CY and Ariane and originally developed at ETH Zurich. | The CORE-V MCU serves as a minimal basis to demonstrate the capabilities of the OpenHW Group CORE-V CV32E4 and CVA6 microprocessors, previously known as RI5CY and Ariane and originally developed at ETH Zurich. | ||
The SoC consists of a minimal set of peripherals (CLINT, PLIC) as well as I/O (UART). | The SoC consists of a minimal set of peripherals (CLINT, PLIC) as well as I/O (UART). | ||
This MCU, called Heroino, is the successor of the famous PULPino, developed to demonstrate the capability of the RI5CY core. Differently from the more complex PULPissimo MCU, whose goal is to be a performant, state-of-the-art MCU, PULPino and Heroino have the goals of make the user experience easy and standard, with industrial standard peripherals subsystem and software (as freeRTOS). | This MCU, called Heroino, is the successor of the famous PULPino, developed to demonstrate the capability of the RI5CY core. Differently from the more complex PULPissimo MCU, whose goal is to be a performant, state-of-the-art MCU, PULPino and Heroino have the goals of make the user experience easy and standard, with industrial standard peripherals subsystem and software (as freeRTOS). | ||
| − | |||
| − | Embedded Domain - OBI based | + | ==Feature Set== |
| − | Configurable CV32E40P instance. | + | |
| − | Default parameters chosen to be compatible with the RTL freeze version. | + | *Embedded Domain - OBI based |
| − | TCDM (tightly coupled data memory) | + | **Configurable CV32E40P instance. |
| − | Shared, banked, memory for high-performance memory access by both the instruction and the data ports of CV32. | + | ***Default parameters chosen to be compatible with the RTL freeze version. |
| − | Application Domain - AXI based | + | **TCDM (tightly coupled data memory) |
| − | Configurable CVA6 instance | + | ***Shared, banked, memory for high-performance memory access by both the instruction and the data ports of CV32. |
| − | Peripheral Domain - APB based | + | *Application Domain - AXI based |
| − | PLIC and CLINT interrupt controllers | + | **Configurable CVA6 instance |
| − | A few key peripherals: | + | *Peripheral Domain - APB based |
| − | UART from lowRISC | + | **PLIC and CLINT interrupt controllers |
| − | PLIC from lowRISC | + | **A few key peripherals: |
| − | [Quad-SPI (to be developed)] optional | + | ***UART from lowRISC |
| − | RISC-V Debug from ETH | + | ***PLIC from lowRISC |
| + | ***[Quad-SPI (to be developed)] optional | ||
| + | **RISC-V Debug from ETH | ||
CLINT from ETH | CLINT from ETH | ||
Custom generated bootrom | Custom generated bootrom | ||
Revision as of 14:59, 6 February 2021
Introduction
The CORE-V MCU serves as a minimal basis to demonstrate the capabilities of the OpenHW Group CORE-V CV32E4 and CVA6 microprocessors, previously known as RI5CY and Ariane and originally developed at ETH Zurich. The SoC consists of a minimal set of peripherals (CLINT, PLIC) as well as I/O (UART). This MCU, called Heroino, is the successor of the famous PULPino, developed to demonstrate the capability of the RI5CY core. Differently from the more complex PULPissimo MCU, whose goal is to be a performant, state-of-the-art MCU, PULPino and Heroino have the goals of make the user experience easy and standard, with industrial standard peripherals subsystem and software (as freeRTOS).
Feature Set
- Embedded Domain - OBI based
- Configurable CV32E40P instance.
- Default parameters chosen to be compatible with the RTL freeze version.
- TCDM (tightly coupled data memory)
- Shared, banked, memory for high-performance memory access by both the instruction and the data ports of CV32.
- Configurable CV32E40P instance.
- Application Domain - AXI based
- Configurable CVA6 instance
- Peripheral Domain - APB based
- PLIC and CLINT interrupt controllers
- A few key peripherals:
- UART from lowRISC
- PLIC from lowRISC
- [Quad-SPI (to be developed)] optional
- RISC-V Debug from ETH
CLINT from ETH Custom generated bootrom DMA Efficient memory transfers. It can be based on the one from PULP Accelerator A configurable number of ports into the TCDM Continuous Integration Checks and Artifact generation Verilator compile and run. Check dependencies up-to-date. Check commit messages and commit formats. Verible lint. Any commercial tool lints which we are going to use. Bit-stream generation, at least for the web-pack FPGAs. Store bit-streams as downloadable artifacts on the repository. Repo organization Flat dependencies, use the vendor.py tool Auto-generated and self-hosted documentation. Linear GIT history. PRs are squashed and committed as one change.
File hierarchy (no submodules, no sub-trees, etc.):
doc: Documentation hw: RTL source directory vendor: Vendored external sources axi: AXI dependency apb: APB dependency ... system: src: Top-level and auxiliary files for the core-v-mcu system. sw: Generated linker scripts and file headers. sw: Software repository vendor: compliance_tests riscv-tests README.md: Link to other documentation, small getting-started guide. LICENSE python-requirements.txt: List of Python requirements to be installed.
