Difference between revisions of "Heroino: Design of the next CORE-V Microcontroller"

Revision as of 23:46, 6 February 2021

Introduction

The CORE-V MCU serves as a minimal basis to demonstrate the capabilities of the OpenHW Group CORE-V CV32E4 and CVA6 microprocessors, previously known as RI5CY and Ariane and originally developed at ETH Zurich. The SoC consists of a minimal set of peripherals (CLINT, PLIC) as well as I/O (UART). This MCU, called Heroino, is the successor of the famous PULPino, developed to demonstrate the capability of the RI5CY core. Differently from the more complex PULPissimo MCU, whose goal is to be a performant, state-of-the-art MCU, PULPino and Heroino have the goals of make the user experience easy and standard, with industrial standard peripherals subsystem and software (as freeRTOS).

Feature Set

• Embedded Domain - OBI based
  • Configurable CV32E40P instance.
    • Default parameters chosen to be compatible with the RTL freeze version.
  • TCDM (tightly coupled data memory)
    • Shared, banked, memory for high-performance memory access by both the instruction and the data ports of CV32.
• Application Domain - AXI based
  • Configurable CVA6 instance
• Peripheral Domain - APB based
  • PLIC and CLINT interrupt controllers
  • A few key peripherals:
    • UART from lowRISC
    • PLIC from lowRISC
    • [Quad-SPI (to be developed)] optional
    • RISC-V Debug from ETH
    • CLINT from ETH
    • Custom generated bootrom
• DMA
  • Efficient memory transfers. It can be based on the one from PULP
• Accelerator
  • A configurable number of ports into the TCDM

Continuous Integration Checks and Artifact generation

• Verilator compile and run.
• Check dependencies up-to-date.
• Check commit messages and commit formats.
• Verible lint.
• Any commercial tool lints which we are going to use.
• Bit-stream generation, at least for the web-pack FPGAs.
  • Store bit-streams as downloadable artifacts on the repository.

Repo organization

• Flat dependencies, use the vendor.py tool
• Auto-generated and self-hosted documentation.
• Linear GIT history. PRs are squashed and committed as one change.

File hierarchy (no submodules, no sub-trees, etc.):

• doc: Documentation
• hw: RTL source directory
  • vendor: Vendored external sources
    • axi: AXI dependency
    • apb: APB dependency
    • ...
  • system:
    • src: Top-level and auxiliary files for the core-v-mcu system.
    • sw: Generated linker scripts and file headers.
• sw: Software repository
  • vendor:
    • compliance_tests
    • riscv-tests
• README.md: Link to other documentation, small getting-started guide.
• LICENSE
• python-requirements.txt: List of Python requirements to be installed.

Architecture

The Embedded Domain is shown to the left. The OBI crossbar has the memory banks and one port to the AXI crossbar as slaves, and it has the CV32E4, the AXI crossbar and the DMA as master. The banked memory provides the necessary throughput to efficiently serve the instruction and data port of the core as well as the bandwidth requirements of the DMA and the Application domain. The Application domain is based on AXI and it contains the CVA6 core and the DMA as masters. The peripheral subsystem is based on APB and contains the basic peripherals as well as the boot ROM. The JTAG is attached to the RISC-V Debug module, which is a master of the application domain subsystem.

The register interface comes with support for automatically generating register maps based on LowRISC OpenTitan’s reggen tool and can be adapted to APB. This implies that we can very easily support the same set of verified peripherals as in LowRISC OpenTitan.

Wishlist

Future: SPI, SDIO, Camera IF needs DMA, I2C, PWM, GPIO New DMA linked-list of descriptors, ARM DMA 2031 Configurability