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Low-power Clock Generation Solutions for 65nm Technology

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Short Description

At the IIS we are working on a new family of ultra low power processors called PULP (Parallel Ultra Low Powwer Platform). We have started using the UMC65nm technology for the majority of student projects and are planning a series of PULP chips in this technology. Depending on the operating voltage, the clock rate of such a processor will be between 100 and 800 MHz. In this work, a low power clock generation solution is required that can provide the required clock signal for the internal operation from a stable external clock source in the range of 20 to 50 MHz. The thesis will first compare available solutions Analog PLL, Digital PLL in terms of power efficiency, flexibility, stability under different operating conditions. Then the most promising approaches will be chosen and transferred into a circuit design. The clocking solution will then be synthesized/layouted and integrated together with a working PULP cluster for verification.

In a second stage we will investigate methods that will allow us to provide multiple different clock frequencies for dynamic voltage and frequency switching applications.

We expect to use the result of this work in all subsequent PULP chips on the 65nm process node.

Status: Available

Looking for 1-2 Master students
Contact: Frank K. Gürkaynak
Thomas Burger
Lianbo Wu

Prerequisites

VLSI I
VLSI II (recommended)
AIC

Character

20% Theory
40% ASIC Design
40% EDA tools

Professor

Luca Benini

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