Difference between revisions of "Nils Wistoff"
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Latest revision as of 18:59, 30 October 2020
Contents
Contact
- Office: ETZ J85
- E-Mail: nwistoff@iis.ee.ethz.ch
- Phone: +41 44 632 06 75
Interests
- Processor Design
- Secure Computer Architectures
- Operating Systems
Projects
Available Projects
- FPGA mapping of RPC DRAM
- Implementation of a Coherent Application-Class Multicore System (1-2S)
- Resource Partitioning of RPC DRAM
- Serverless Benchmarks on RISC-V (M)
- IP-Based SoC Generation and Configuration (1-3S/B)
Projects In Progress
Completed Projects
- Resource Partitioning of Caches
- A Flexible FPGA-Based Peripheral Platform Extending Linux-Capable Systems on Chip (1-3S/B)
- Hypervisor Extension for Ariane (M)
- Implementation of an AES Hardware Processing Engine (B/S)
- Multi issue OoO Ariane Backend (M)
- Towards the Ariane Desktop: Display Output for Ariane on FPGA under Linux (S/B/G)
- Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S)
- Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S)
- PULP in space - Fault Tolerant PULP System for Critical Space Applications
- A Snitch-based Compute Accelerator for HERO (M/1-2S)
