Difference between revisions of "PULP’s CLIC extensions for fast interrupt handling"
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− | <!-- Integration of | + | <!-- Integration and implementation of PULP’s CLIC in PULPissimo --> |
[[Category:Digital]] | [[Category:Digital]] | ||
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= Introduction = | = Introduction = | ||
− | + | Today’s real-time systems require fast interrupt handling to manage asynchronous requests coming from the surrounding environment. This means that the underlying HW should guarantee a fast propagation of the interrupt line towards the core, with a per-interrupt, fine-grained control over each line, and support interrupt preemption and nesting according to each event priority. | |
− | |||
= Project = | = Project = | ||
− | PULPissimo is an open-source, single core RISC-V microcontroller [ | + | PULPissimo is an open-source, single core RISC-V microcontroller [4] developed by PULP that hosts an industrial-grade processor, namely CV32E40P [3]. |
+ | RISC-V Core Local Interrupt Controller (CLIC) [2] is a standardized interrupt controller for RISC-V core subsuming the original RISC-V local interrupt scheme (CLINT). It promises pre-emptive, low-latency, vectored, priority/level based interrupts. | ||
− | The goal of this project is to replace | + | The goal of this project is to replace the current interrupt handler in PULPissimo with the CLIC. |
− | * Study | + | |
− | + | In particular: | |
− | * Integrate | + | |
+ | * Study CLIC reference specifications [2] and PULP’s CLIC implementation [1] | ||
+ | * Integrate PULP’s CLIC into PULPissimo to replace the existing interrupt controller | ||
* Verify basic functional correctness in simulation | * Verify basic functional correctness in simulation | ||
− | * Synthesize the | + | * Investigate HW/SW extensions based on known CLIC implementations, such as [5] and [6] |
+ | * Synthesize the design, giving particular attention to the CLIC overhead with respect to the original baseline | ||
* ASIC Backend flow towards PULPissimo SoC tapeout | * ASIC Backend flow towards PULPissimo SoC tapeout | ||
Line 52: | Line 55: | ||
= References = | = References = | ||
− | [1] https://github.com/ | + | [1] https://github.com/pulp-platform/clic |
− | + | [2] https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc | |
− | [ | + | [3] https://github.com/openhwgroup/cv32e40p |
− | + | [4] https://github.com/pulp-platform/pulpissimo | |
− | [ | + | [5] https://github.com/bluewww/opene906 |
− | + | [6] https://doc.nucleisys.com/nuclei_spec/isa/eclic.html | |
− | [ |
Revision as of 16:12, 31 January 2022
Contents
Overview
Status: Available
- Type: Semester Thesis
- Professor: Prof. Dr. L. Benini
- Supervisors:
Introduction
Today’s real-time systems require fast interrupt handling to manage asynchronous requests coming from the surrounding environment. This means that the underlying HW should guarantee a fast propagation of the interrupt line towards the core, with a per-interrupt, fine-grained control over each line, and support interrupt preemption and nesting according to each event priority.
Project
PULPissimo is an open-source, single core RISC-V microcontroller [4] developed by PULP that hosts an industrial-grade processor, namely CV32E40P [3]. RISC-V Core Local Interrupt Controller (CLIC) [2] is a standardized interrupt controller for RISC-V core subsuming the original RISC-V local interrupt scheme (CLINT). It promises pre-emptive, low-latency, vectored, priority/level based interrupts.
The goal of this project is to replace the current interrupt handler in PULPissimo with the CLIC.
In particular:
- Study CLIC reference specifications [2] and PULP’s CLIC implementation [1]
- Integrate PULP’s CLIC into PULPissimo to replace the existing interrupt controller
- Verify basic functional correctness in simulation
- Investigate HW/SW extensions based on known CLIC implementations, such as [5] and [6]
- Synthesize the design, giving particular attention to the CLIC overhead with respect to the original baseline
- ASIC Backend flow towards PULPissimo SoC tapeout
Character
- 15% Literature / architecture review
- 30% RTL implementation
- 30% Backend
- 25% Evaluation
Prerequisites
- Experience with digital design in SystemVerilog as taught in VLSI I
- Must have visited VLSI II in a previous semester or take it alongside the thesis
References
[1] https://github.com/pulp-platform/clic [2] https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc [3] https://github.com/openhwgroup/cv32e40p [4] https://github.com/pulp-platform/pulpissimo [5] https://github.com/bluewww/opene906 [6] https://doc.nucleisys.com/nuclei_spec/isa/eclic.html