Reconfigurability of SHA-3 candidates
From iis-projects
Revision as of 09:37, 17 January 2014 by Kgf (talk | contribs) (Created page with "thumb|250px ==Short Description== In December 2010, the 5 finalists of the SHA-3 competition were announced. The SHA-3 candi...")
Contents
Short Description
In December 2010, the 5 finalists of the SHA-3 competition were announced. The SHA-3 candidates all need to provide a 256-Bit and a 512-Bit mode. The goal of this project is to implement for each of these candidates a reconfigurable core that is capable of calculating 256-Bit and 512-Bit hashes with the same hardware.
Status: Available
- Looking for 1-2 Semester/Master students
- Contact: Christoph Keller
Prerequisities
- VLSI I
- Interest in Cryptography
Character
- 20% Theory
- 55% VHDL Design
- 25% ASIC Implementation
