User contributions
From iis-projects
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- 15:51, 17 November 2021 (diff | hist) . . (-4) . . Transforming MemPool into a CGRA (M) (current)
- 15:50, 17 November 2021 (diff | hist) . . (-2) . . Multi issue OoO Ariane Backend (M) (current)
- 15:43, 17 November 2021 (diff | hist) . . (+3,121) . . N Augmenting Our IPs with AXI Stream Extensions (M/1-2S) (Created page with "<!-- Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S) --> Category:Digital Category:High Performance SoCs Category:Computer Architecture Catego...")
- 20:13, 15 November 2021 (diff | hist) . . (+3) . . Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S) (→Status: Reserved)
- 20:02, 15 November 2021 (diff | hist) . . (-50) . . IP-Based SoC Generation and Configuration (1-3S/B) (→Introduction)
- 19:47, 15 November 2021 (diff | hist) . . (+766) . . IP-Based SoC Generation and Configuration (1-3S/B)
- 13:08, 15 November 2021 (diff | hist) . . (-83) . . Analog Compute-in-Memory Accelerator Interface and Integration
- 13:04, 15 November 2021 (diff | hist) . . (-1) . . High Performance SoCs (→Who are we)
- 21:35, 4 October 2021 (diff | hist) . . (+3) . . m Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S)
- 22:18, 14 September 2021 (diff | hist) . . (-2) . . Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S)
- 17:03, 9 September 2021 (diff | hist) . . (-3) . . m High Performance SoCs (→Projects)
- 15:48, 9 September 2021 (diff | hist) . . (+654) . . High Performance SoCs (→Projects)
- 15:10, 10 August 2021 (diff | hist) . . (0) . . m Exploration and Hardware Acceleration of Intra-Layer Mixed-Precision QNNs (→Status: Available)
- 15:08, 10 August 2021 (diff | hist) . . (+3,465) . . N Exploration and Hardware Acceleration of Intra-Layer Mixed-Precision QNNs (Created page with "<!-- Exploration and Hardware Acceleration of Intra-Layer Mixed-Precision QNNs --> Category:Digital Category:Deep Learning Projects Category:Acceleration_and_Transp...")
- 14:52, 10 August 2021 (diff | hist) . . (+45) . . Universal Stream Semantic Registers for Snitch (1S)
- 13:25, 10 August 2021 (diff | hist) . . (+7) . . m Evaluating memory access pattern specializations in OoO, server-grade cores (M) (current)
- 13:24, 10 August 2021 (diff | hist) . . (-29) . . Universal Stream Semantic Registers for Snitch (1S)
- 13:24, 10 August 2021 (diff | hist) . . (-27) . . Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S)
- 11:29, 10 August 2021 (diff | hist) . . (+4,032) . . N Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S) (Created page with "<!-- Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S) --> <!-- TODO: remove safety Category:Digital Category:High Performance SoCs Category:Computer...")
- 11:27, 10 August 2021 (diff | hist) . . (+10) . . m Universal Stream Semantic Registers for Snitch (1S)
- 11:21, 10 August 2021 (diff | hist) . . (+3,205) . . N Universal Stream Semantic Registers for Snitch (1S) (Created page with "<!-- Universal Stream Semantic Registers for Snitch (1S) --> <!-- TODO: unlock safety Category:Digital Category:High Performance SoCs Category:Computer Architecture...")
- 11:07, 10 August 2021 (diff | hist) . . (+124) . . Digital (→Completed Projects)
- 19:57, 29 July 2021 (diff | hist) . . (+9) . . m SystemVerilog formatter for our LowRISC-based guidelines (2-3G) (current)
- 15:25, 9 July 2021 (diff | hist) . . (-4) . . Physical Implementation of Ara, PULP's Vector Machine (1-2S) (current)
- 15:21, 9 July 2021 (diff | hist) . . (-21) . . Towards the Ariane Desktop: Display Output for Ariane on FPGA under Linux (S/B/G) (current)
- 15:21, 9 July 2021 (diff | hist) . . (-4) . . Ottocore: A Minimal RISC-V Core Designed for Teaching (B/2G) (current)
- 15:20, 9 July 2021 (diff | hist) . . (-4) . . LLVM and DaCe for Snitch (1-2S) (current)
- 15:19, 9 July 2021 (diff | hist) . . (-19) . . Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S) (current)
- 15:19, 9 July 2021 (diff | hist) . . (-2) . . Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S) (current)
- 15:18, 9 July 2021 (diff | hist) . . (-2) . . m A Snitch-Based SoC on iCE40 FPGAs (1-2S/B) (current)
- 15:18, 9 July 2021 (diff | hist) . . (0) . . m An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S) (current)
- 15:17, 9 July 2021 (diff | hist) . . (-2) . . An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)
- 15:17, 9 July 2021 (diff | hist) . . (-2) . . A Snitch-Based SoC on iCE40 FPGAs (1-2S/B)
- 15:19, 20 April 2021 (diff | hist) . . (+24) . . High Performance SoCs (→Who are we)
- 23:31, 1 April 2021 (diff | hist) . . (+8) . . Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S)
- 23:31, 1 April 2021 (diff | hist) . . (+30) . . N Category:Lbertaccini (Redirected page to User:Lbertaccini) (current)
- 23:27, 1 April 2021 (diff | hist) . . (+2) . . Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S)
- 15:40, 15 March 2021 (diff | hist) . . (-4) . . m A Flexible Peripheral System for High-Performance Systems on Chip (M) (current)
- 13:28, 7 March 2021 (diff | hist) . . (+10,678) . . N Online Learning of User Features (1S) (Created page with "<!-- Online Learning of User Features (1S) --> = Overview = == Status: Available == * Type: Semester Thesis * Professor: Prof. Dr. L. Benini * Supervisors: ** Cristian Ciof...")
- 13:17, 7 March 2021 (diff | hist) . . (0) . . N File:KWS.png (current)
- 13:17, 7 March 2021 (diff | hist) . . (0) . . N File:KWS+UE.png (current)
- 20:12, 15 February 2021 (diff | hist) . . (+1) . . LLVM and DaCe for Snitch (1-2S) (→Status: In progress)
- 20:07, 15 February 2021 (diff | hist) . . (+11,100) . . N LLVM and DaCe for Snitch (1-2S) (Created page with "<!-- LLVM and DaCe for Snitch (1-2S) --> = Overview = == Status: In progress == * Type: Semester Thesis * Semester: Spring Semester 2021 * Student: Noah Hütter * Start: Ma...")
- 20:02, 15 February 2021 (diff | hist) . . (+76) . . Quest for the smallest Turing-complete core (2-3G) (Redirected page to Ottocore: A Minimal RISC-V Core Designed for Teaching (B/2G)) (current)
- 19:57, 15 February 2021 (diff | hist) . . (+10,538) . . N Ottocore: A Minimal RISC-V Core Designed for Teaching (B/2G) (Created page with "<!-- Ottocore: A Minimal RISC-V Core Designed for Teaching (B/2G) --> = Overview = == Status: In progress == * Type: Bachelor's Thesis * Semester: Spring Semester 2021 * St...")
- 18:36, 15 February 2021 (diff | hist) . . (+36) . . m An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)
- 18:26, 15 February 2021 (diff | hist) . . (0) . . m Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S)
- 18:25, 15 February 2021 (diff | hist) . . (+3) . . Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S)
- 18:25, 15 February 2021 (diff | hist) . . (+86) . . Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S) (→Status: Available)
- 23:59, 6 February 2021 (diff | hist) . . (-4) . . A Snitch-based Compute Accelerator for HERO (M/1-2S) (current)
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