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Showing below up to 100 results in range #1 to #100.
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- High Performance Cellular Receivers in Very Advanced CMOS (2 revisions)
- Implementation of a 2-D model for Li-ion batteries (2 revisions)
- Benchmarking a heterogeneous 217-core MPSoC on HPC applications (2 revisions)
- Smart Patch For Heath Care And Rehabilitation (2 revisions)
- A Post-Simulation Trace-Based RISC-V GDB Debugging Server (2 revisions)
- Ultrasound measurement of microbubble stiffness for in situ detection of protease activity in clinical settings (2 revisions)
- Accelerators for object detection and tracking (2 revisions)
- Test project (2 revisions)
- Triple-Core PULPissimo (2 revisions)
- Deep Unfolding of Iterative Optimization Algorithms (2 revisions)
- On-Device Training Sparse Sub-Tensor Update Scheme Optimization for CNN-based tasks (2 revisions)
- An Efficient Compiler Backend for Snitch (1S/B) (2 revisions)
- Successive Interference Cancellation for 3G Downlink (2 revisions)
- Optimal System Duty Cycling (2 revisions)
- Accurate deep learning inference using computational memory (2 revisions)
- Quantum Transport Modeling of Interband Cascade Lasers (ICL) (2 revisions)
- Autonomous Smart Sensors for IoT (2 revisions - redirect page)
- BirdGuard (2 revisions)
- Mixed Signal IC Design (2 revisions)
- System on Chips for IoTs (2 revisions - redirect page)
- Data Mapping for Unreliable Memories (2 revisions)
- High-Resolution, Calibrated Folding ADCs (2 revisions)
- PREM Intervals and Loop Tiling (2 revisions)
- Improving SystemVerilog Support for Free And Open-Source EDA Tools (1-3S/B) (2 revisions)
- AXI-based Network on Chip (NoC) system (2 revisions)
- Design of a Reconfigurable Vector Processor Cluster for Area Efficient Radar Processing (1M) (2 revisions)
- Audio Visual Speech Recognition (1S/1M) (2 revisions)
- Kinetic Energy Harvesting For Autonomous Smart Watches (2 revisions)
- Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)) (2 revisions)
- Near-Optimal Reduced-Complexity Sequence Detectors for TD-HSPA (2 revisions)
- Low Precision Ara for ML (2 revisions)
- Christoph Leitner (2 revisions)
- Development Of A Test Bed For Ultrasonic Transducer Characterization (2 revisions - redirect page)
- RazorEDGE (2 revisions - redirect page)
- Exploitation of Inherent Error Resilience of Wireless Systems under Unreliable Silicon (2 revisions)
- Towards Flexible and Printable Wearables (2 revisions)
- A Demonstrator of Non-Synchronized Hyperdimensional Body Area Networks (2 revisions)
- Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1-3S/B) (2 revisions)
- Ab-initio Simulation of Strained Thermoelectric Materials (2 revisions)
- Wake Up Radio For Energy Efficient Communication System and IC Design (2 revisions)
- Enhancing Our DMA Engine With Virtual Memory (M/1-3S/B) (2 revisions)
- Convolution Neural Networks on our Ultra-Low Power Mult-Core Plattform PULP (2 revisions)
- Network-off-Chip (M) (2 revisions)
- Design of low mismatch DAC used for VAD (2 revisions)
- Adaptively Controlled Hysteresis Curve Tracer For Polymer Piezoelectrics (1 S/B) (2 revisions - redirect page)
- Research (2 revisions)
- Evaluating memory access pattern specializations in OoO, server-grade cores (M) (2 revisions)
- Short Range Radars For Biomedical Application (2 revisions)
- Low Resolution Neural Networks (2 revisions)
- Norbert Felber (2 revisions)
- Skin Coupling Media Characterization For Fitness Tracker Applications (1 B/S) (2 revisions)
- Design Of A Biomarker Assay Based On Responsive Magnetic Nanoparticles (2 revisions)
- On - Device Continual Learning for Seizure Detection on GAP9 (2 revisions)
- Ultrasound (2 revisions)
- Network-on-Chip for coherent and non-coherent traffic (M) (2 revisions)
- Using Motion Sensors to Support Indoor Localization (2 revisions)
- Analog Layout Engine (2 revisions)
- Autonomus Drones With Novel Sensors And Ultra Wide Band (2 revisions)
- Modeling High Bandwidth Memory for Rapid Design Space Exploration (1-3S/B) (2 revisions)
- Flexible Front-End Circuit for Biomedical Data Acquisition (2 revisions)
- Development Of An FPGA-Based Optoacoustic Image Reconstruction Platform for Clinical Applications (2 revisions)
- Power Saver Mode for Cellular Internet of Things Receivers (2 revisions)
- Design Review (2 revisions)
- High Throughput Turbo Decoder Design (2 revisions)
- Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (B/1-3S) (2 revisions)
- Weak-strong massive MIMO communication with low-resolution ADCs (2 revisions)
- Securing Block Ciphers against SCA and SIFA (2 revisions)
- Neural Architecture Search using Reinforcement Learning and Search Space Reduction (2 revisions)
- Hardware Support for IDE in Multicore Environment (2 revisions)
- Design study of tunneling transistors based on a core/shell nanowire structures (2 revisions)
- LightProbe - 192cha Multiplexer Stage (Rigid-Flex-PCB Project) (2 revisions)
- Signal Acquisition and Clock Offset Compensation for High-Rate Pulse UWB PHYs (2 revisions)
- Coding Guidelines (2 revisions)
- Cryptography (2 revisions)
- Design of a CAN Interface to Enable Reliable Sensors-to-Processors Communication for Automotive-oriented Embedded Applications (1M) (2 revisions)
- Alias-Free Oscillator Synchronization for Arbitrary Waveforms (2 revisions)
- Towards Self-Sustainable Unmanned Aerial Vehicles (2 revisions)
- A Flexible Peripheral System for High-Performance Systems on Chip (M) (2 revisions)
- Wearable Smart Camera With Deep Learning Algorithms For Automatic Detecion (2 revisions)
- Wireless Sensing With Long Range Comminication (LoRa) (2 revisions)
- RISC-V base ISA for ultra-low-area cores (2-3G) (2 revisions)
- Time Synchronization for 3G Mobile Communications (2 revisions)
- PULP Freertos with LLVM (2 revisions)
- Prasadar (2 revisions)
- Assessment of novel photovoltaic architectures by circuit simulation (2 revisions)
- SSR combined with FREP in LLVM/Clang (2 revisions)
- Computation of Phonon Bandstructure in III-V Nanostructures (2 revisions)
- Project Meetings (2 revisions)
- Finalizing and Releasing Our Open-source AXI4 IPs (1-3S/B/2-3G) (2 revisions)
- Neural Networks Framwork for Embedded Plattforms (2 revisions)
- Herschmi (2 revisions)
- Optogenetics And Game Theory Applied To Small Side Bird Using Smart Sensing (2 revisions)
- VLSI Implementation Polar Decoder using High Level Synthesis (2 revisions)
- LightProbe - CNN-Based-Image-Reconstruction (2 revisions)
- Coherence-Capable Write-Back L1 Data Cache for Ariane (M) (2 revisions)
- Frank K. Gürkaynak (2 revisions)
- NORX - an AEAD algorithm for the CAESAR competition (2 revisions)
- Project Plan (2 revisions)
- Integrating Hardware Accelerators into Snitch 1S (2 revisions - redirect page)
- Realtime Gaze Tracking on Siracusa (2 revisions)
