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Showing below up to 20 results in range #21 to #40.
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- Improving SystemVerilog Support for Free And Open-Source EDA Tools (1-3S/B) (2 revisions)
- Data Mapping for Unreliable Memories (2 revisions)
- High-Resolution, Calibrated Folding ADCs (2 revisions)
- PREM Intervals and Loop Tiling (2 revisions)
- Audio Visual Speech Recognition (1S/1M) (2 revisions)
- Kinetic Energy Harvesting For Autonomous Smart Watches (2 revisions)
- Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)) (2 revisions)
- Near-Optimal Reduced-Complexity Sequence Detectors for TD-HSPA (2 revisions)
- AXI-based Network on Chip (NoC) system (2 revisions)
- Design of a Reconfigurable Vector Processor Cluster for Area Efficient Radar Processing (1M) (2 revisions)
- Low Precision Ara for ML (2 revisions)
- Christoph Leitner (2 revisions)
- Development Of A Test Bed For Ultrasonic Transducer Characterization (2 revisions - redirect page)
- RazorEDGE (2 revisions - redirect page)
- Exploitation of Inherent Error Resilience of Wireless Systems under Unreliable Silicon (2 revisions)
- Wake Up Radio For Energy Efficient Communication System and IC Design (2 revisions)
- Enhancing Our DMA Engine With Virtual Memory (M/1-3S/B) (2 revisions)
- Convolution Neural Networks on our Ultra-Low Power Mult-Core Plattform PULP (2 revisions)
- Network-off-Chip (M) (2 revisions)
- Towards Flexible and Printable Wearables (2 revisions)
