Long pages

Showing below up to 50 results in range #21 to #70.

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21. (hist) ‎Ultra-low power processor design ‎[10,511 bytes]
22. (hist) ‎ASR-Waveformer ‎[10,179 bytes]
23. (hist) ‎Implementing DSP Instructions in Banshee (1S) ‎[10,092 bytes]
24. (hist) ‎On-Device Federated Continual Learning on Nano-Drone Swarms ‎[10,073 bytes]
25. (hist) ‎Hyperdimensional Computing ‎[9,993 bytes]
26. (hist) ‎Graph neural networks for epileptic seizure detection ‎[9,773 bytes]
27. (hist) ‎Fast Simulation of Manycore Systems (1S) ‎[9,741 bytes]
28. (hist) ‎Bringing XNOR-nets (ConvNets) to Silicon ‎[9,740 bytes]
29. (hist) ‎Biomedical Circuits, Systems, and Applications ‎[9,550 bytes]
30. (hist) ‎IBM Research ‎[9,475 bytes]
31. (hist) ‎Audio Visual Speech Recognition (1S/1M) ‎[9,414 bytes]
32. (hist) ‎Audio Visual Speech Separation (1S/1M) ‎[9,412 bytes]
33. (hist) ‎ISA extensions in the Snitch Processor for Signal Processing (M) ‎[9,151 bytes]
34. (hist) ‎Interfacing PULP with a Brain-Inspired Ultra-Low Power Spiking Cochlea ‎[9,139 bytes]
35. (hist) ‎Design and Implementation of a Convolutional Neural Network Accelerator ASIC ‎[9,080 bytes]
36. (hist) ‎On - Device Continual Learning for Seizure Detection on GAP9 ‎[9,053 bytes]
37. (hist) ‎Rethinking our Convolutional Network Accelerator Architecture ‎[9,007 bytes]
38. (hist) ‎Extreme-Edge Experience Replay for Keyword Spotting ‎[8,980 bytes]
39. (hist) ‎Heroino: Design of the next CORE-V Microcontroller ‎[8,937 bytes]
40. (hist) ‎Manycore System on FPGA (M/S/G) ‎[8,654 bytes]
41. (hist) ‎Continual Learning for Adaptive EEG Monitoring in Epileptic Seizure Detection ‎[8,413 bytes]
42. (hist) ‎MCU Bus and Memory Generator: implementation of a Highly Configurable bus and memory subsystem for a RISC-V based microcontroller. ‎[8,411 bytes]
43. (hist) ‎A Snitch-Based SoC on iCE40 FPGAs (1-2S/B) ‎[8,380 bytes]
44. (hist) ‎An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S) ‎[8,317 bytes]
45. (hist) ‎High-speed Scene Labeling on FPGA ‎[8,302 bytes]
46. (hist) ‎Design of Scalable Event-driven Neural-Recording Digital Interface ‎[8,231 bytes]
47. (hist) ‎A reduction-capable AXI XBAR for fast M-to-1 communication (1M) ‎[8,184 bytes]
48. (hist) ‎FFT-based Convolutional Network Accelerator ‎[8,120 bytes]
49. (hist) ‎Improved State Estimation on PULP-based Nano-UAVs ‎[8,098 bytes]
50. (hist) ‎Improving our Smart Camera System ‎[8,056 bytes]
51. (hist) ‎Peripheral Event Linking System for Real-time Capable Energy Efficient SoCs ‎[8,002 bytes]
52. (hist) ‎Practical Reconfigurable Intelligent Surfaces (RIS) ‎[7,979 bytes]
53. (hist) ‎Floating-Point Divide & Square Root Unit for Transprecision ‎[7,966 bytes]
54. (hist) ‎Spatz grows wings: Physical Implementation of a Vector-Powered Manycore System (2S) ‎[7,927 bytes]
55. (hist) ‎RISC-V based Implementation of Secure Ranging According to IEEE 802.15.4z UWB ‎[7,824 bytes]
56. (hist) ‎GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S) ‎[7,808 bytes]
57. (hist) ‎Mixed-Precision Neural Networks for Brain-Computer Interface Applications ‎[7,773 bytes]
58. (hist) ‎Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S) ‎[7,696 bytes]
59. (hist) ‎Self-Supervised User Positioning in Cell-Free Massive MIMO Systems ‎[7,691 bytes]
60. (hist) ‎Towards the Ariane Desktop: Display Output for Ariane on FPGA under Linux (S/B/G) ‎[7,663 bytes]
61. (hist) ‎A RISC-V ISA Extension for Scalar Chaining in Snitch (M) ‎[7,624 bytes]
62. (hist) ‎XNORLAX: Fused XNOR-LATCH Custom-Standard-Cell-Based Processing-in-Memory ‎[7,358 bytes]
63. (hist) ‎Neural Network Algorithms and Interfaces with Accelerators for Embedded Platforms with Real World Applications ‎[7,337 bytes]
64. (hist) ‎Smart Patch For Heath Care And Rehabilitation ‎[7,308 bytes]
65. (hist) ‎Cell-Free mmWave Massive MIMO Communication ‎[7,265 bytes]
66. (hist) ‎Weekly Reports ‎[7,258 bytes]
67. (hist) ‎An all Standard-Cell Based Energy Efficient HW Accelerator for DSP and Deep Learning Applications ‎[7,241 bytes]
68. (hist) ‎Integrating Ultrasound Technology into a Fitness Tracking Device (1M, 2 B/S) ‎[7,201 bytes]
69. (hist) ‎A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S) ‎[7,164 bytes]
70. (hist) ‎Baseband Meets CPU ‎[7,100 bytes]

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