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• High-speed Scene Labeling on FPGA
  ...of recognizing and classifying objects in a scene. Many popular algorithms in this area require the evaluations of multiple layers of filter banks. Almos ...are codesign work is much more applicable in industry and less constrained in terms of memory and interfaces. If desired by the student, also the use of
  8 KB (1,197 words) - 18:18, 29 August 2016
• Michael Muehlberghuber
  ...an the ones listed below. So just drop me an e-mail or come into my office in order to discuss any security- or cryptography-related topics. ===Projects in Progress===
  1 KB (139 words) - 12:39, 7 November 2017
• Cryptography
  ...eld of cryptography. Feel free to contact them if you want to do a project in this field. <!-- ==Projects in Progress==
  645 bytes (67 words) - 21:04, 24 August 2018
• Time Synchronization for 3G Mobile Communications
  ...are around and which synchronization codes are used. Solving this problem in dedicated hardware will be the topic of this thesis. Synchronization in time will detect the position of the frame boundaries and reveal the Cell I
  3 KB (420 words) - 11:22, 14 April 2016
• PULPonFPGA: Lightweight Virtual Memory Support - Coherency Extensions
  ...on to enable lightweight virtual memory support for many-core accelerators in heterogeneous embedded SoCs. Based on a content-addressable memory (CAM), e ...L. Benini, "Lightweight Virtual Memory Support for Many-Core Accelerators in Heterogeneous Embedded SoCs", ''Proceedings of the 10th International Confe
  4 KB (585 words) - 17:57, 7 November 2017
• PULPonFPGA: Lightweight Virtual Memory Support - Multi-Level TLB
  ...on to enable lightweight virtual memory support for many-core accelerators in heterogeneous embedded SoCs. Based on a content-addressable memory (CAM), e ...with a multi-level TLB and lightweight hardware support for TLB management in order to support dynamic self-updating of the TLB without frequent host int
  4 KB (554 words) - 17:57, 7 November 2017
• Autonomous Sensing For Trains In The IoT Era
  ...and railways applications in collaboration with Bombardier that (i) can go in a zero-power but with change status fast when important events are detected
  6 KB (774 words) - 08:36, 23 November 2022
• Switched Capacitor Based Bandgap-Reference
  ...or driven by a posititive to absolute temperature (PTAT) current to result in a temperature independent voltage of about 1.2V. Such a voltage is not comp ...they create an intrinsic voltage ripple that has to be heavily suppressed in the case of a reference.
  4 KB (471 words) - 11:13, 3 May 2018
• Scattering Networks for Scene Labeling
  ...es) were successfully employed in a number of classification tasks [1,3]. In contrast to traditional convolutional neural networks which learn the filt ===Status: {Available, Reserved, In Progress, Completed}===
  4 KB (563 words) - 11:29, 5 February 2016
• Autonomous Smart Watches: Toward an ultra low power microphone detector with events classification
  ...uccess in wearable devices and sensors in several real-world applications. In this project we address the challenges of context recognition on low energy You will investigate the possibility to implement neural network in a ultra low power energy efficient micro-controller (Ambiq Apollo). The mai
  4 KB (507 words) - 12:11, 16 February 2016
• Low Power Neural Network For Multi Sensors Wearable Devices
  ...itoring, and detection of events related to the wearer (e.g. abnormalities in physiological functions, detection of seizures and symptoms, patterns of mo ...rate (e.g. sampling frequency) sufficient for the particular application, in order not to miss the event. However, the rate of occurrence of the event
  7 KB (895 words) - 17:02, 28 July 2017
• GUI-developement for an action-cam-based eye tracking device
  ...ior of novice and expert athletes and the ability to drive in the elderly. In such cases, it is impertinent to record the participants’ behavior under ...t, pause, stop) and all its settings. The live preview should be displayed in the app and a possibility to incorporate a live eye position overlay should
  2 KB (277 words) - 11:10, 3 May 2018
• David J. Mack
  ...ard Karls University in Tübingen, Germany. In 2015, he acquired his Ph.D. in Cognitive and Behavioral Neuroscience at the same university. Since 2015 he If you are interested in eye tracking, biological signal processing or even a neuroscience research
  2 KB (310 words) - 17:41, 31 August 2016
• Improving our Smart Camera System
  ...sify every pixel in an image using convolutional neural networks. However, in the mean time we have developed several new approaches to process the acqui Now we would like to include those in our prototype, and otherwise improve it by building a more compact system,
  8 KB (1,176 words) - 16:26, 30 October 2020
• Implementing Hibernation on the ARM Cortex M0
  ...rocontroller in this environment requires special measurements to be taken in order to avoid restarting the entire task after each power outage. Both scenarios require a mechanism to save a snapshot of the processor state in a non-volatile memory. This mechanism is commonly known as '''hibernation''
  3 KB (390 words) - 11:59, 20 June 2016
• Ultra-Efficient Visual Classification on Movidius Myriad2
  ...lown floating point data that is often unnecessary to achieve good results in trained models. On the other hand, ASICs are often orders of magnitude more ...yriad architecture can provide more than 10 GOPS of processing performance in a power envelope of less than 0.5W. It consists of two general-purpose SPAR
  4 KB (593 words) - 14:57, 30 November 2016
• Efficient Implementation of an Active-Set QP Solver for FPGAs
  Quadratic programming (QP) problems arise in various embedded optimization applications such as model predictive control In this master project you will be working on an efficient FPGA implementation
  4 KB (542 words) - 12:39, 1 June 2017
• FPGA System Design for Computer Vision with Convolutional Neural Networks
  ...of recognizing and classifying objects in a scene. Many popular algorithms in this area require the evaluations of multiple layers of filter banks. Almos ...stem on a FPGA and further improve the accelerator. This is where you come in. We have several aspects which we would like to explore: porting the Origam
  3 KB (397 words) - 18:17, 29 August 2016
• Learning Image Decompression with Convolutional Networks
  In this project, we have developed several ConvNets to remove compression arti ===Status: {Available, Reserved, In Progress, Completed}===
  2 KB (285 words) - 18:16, 29 August 2016
• Covariant Feature Detector on Parallel Ultra Low Power Architecture
  ...ULP) accelerators we are developing the first Computer Vision (CV) library in such domain. ...form designed to operate on a large range of operating voltages, achieving in this way a high level of energy efficiency over a wide range of application
  4 KB (628 words) - 16:16, 20 February 2018
• Gomeza old project3
  ...harvesting applications, sensor nodes are able to store any excess energy in a storage device such as battery or supercapacitor for future use. A correc # Test final design in real-world scenarios
  3 KB (366 words) - 18:04, 28 January 2017
• Bateryless Heart Rate Monitoring
  ...ombination wearable sensors and wireless communication. We are interested in building small wearable, bateryless devices which can perform different dif # Test final design in real-world scenarios.
  3 KB (413 words) - 15:21, 28 January 2016
• Change-based Evaluation of Convolutional Neural Networks
  ...e next (consider a fixed camera and just some people or cars moving around in the scene). This project would look into updating intermediate results only * Interest in computer vision and system engineering
  5 KB (747 words) - 18:04, 29 August 2016
• Rethinking our Convolutional Network Accelerator Architecture
  ...ns such as the synthesis-time fixed filter sizes and room for improvements in terms of energy efficiency. We are looking for your creativity to completel * Interest in VLSI architecture exploration and computer vision
  9 KB (1,263 words) - 18:52, 12 December 2016
• Using Motion Sensors to Support Indoor Localization
  sound, optical, vision, or a combination of them. In the context of low-cost embedded systems, as observed in some previous work [1]. This project abstracts from the specific localizati
  3 KB (426 words) - 11:41, 21 July 2017
• Turbo Equalization for Cellular IoT
  ...ds which is one of the reasons why Turbo equalization is found only seldom in practical receiver implementations today. ...ution can be completely hidden making Turbo equalization a viable solution in practical communication systems.
  3 KB (450 words) - 11:43, 13 November 2018
• PULPonFPGA: Hardware L2 Cache
  ...on to enable lightweight virtual memory support for many-core accelerators in heterogeneous embedded SoCs [1,2]. Recently, we have switched to a new eval ...to be adapted to use the widely adopted AXI4 protocol [6], which has built-in cache control signals that shall be used by your new IP. Besides designing
  5 KB (711 words) - 10:27, 5 November 2019
• NextGenChannelDec
  [[File:channel_decoder_intro.jpg|thumb|400px|Channel Decoder in Today's Communication Systems]] ...TE standard bases for example on Turbo codes, LDPC codes have been adopted in the Wifi standard IEEE802.11n/ac/ax. With that the question arises: What co
  3 KB (402 words) - 15:31, 13 April 2016
• Next Generation Channel Decoder
  [[File:channel_decoder_intro.jpg|thumb|400px|Channel Decoder in Today's Communication Systems]] ...TE standard bases for example on Turbo codes, LDPC codes have been adopted in the WiFi standard IEEE802.11n/ac/ax. With that the question arises: What co
  3 KB (418 words) - 14:01, 13 November 2020
• Implementation of a NB-IoT Positioning System
  ...een satellite and receiver making the location estimation very inaccurate. In indoor environments satellite-based positioning completely fails. Furthermo ...DOA) algorithm the base stations transmit reference signals as illustrated in the figure. The User Equipment (UE) detects the time difference of arrival
  4 KB (555 words) - 16:36, 23 May 2018
• Towards Self Sustainable UAVs
  '''Motivation''' In recent years, the popularity of unmanned aerial vehicles (UAV’s) has soar ...on, it suffers from very large charging times and very short flight times. In this
  3 KB (403 words) - 20:45, 9 August 2016
• PULPonFPGA: Lightweight Virtual Memory Support - Page Table Walker
  ...easily portable to other host CPU architectures, but it cannot be executed in interrupt context which causes substantial scheduling delays and an overall ...orted to a dedicated microcontroller core inside the RAB or be implemented in dedicated hardware. While the first step allows to remove the scheduling de
  5 KB (712 words) - 17:57, 7 November 2017
• PULPonFPGA: Lightweight Virtual Memory Support - Physically Contiguous Memory
  ...nt of the page size of the Linux operating system running on the host CPU. In a student project [4], a second, set-associative IOTLB has been designed wh ...d with the accelerator is placed in this section, requiring a single entry in the first IOTLB only.
  6 KB (866 words) - 13:43, 29 November 2019
• Self-Learning Drones based on Neural Networks
  Neural Nets are achieving record-breaking results in all common machine learning tasks and reached high attention of the machine ...nd made the headline by beating the 2nd best player in the world Lee Sedol in the game Go [1]. A game which were considered to be too complex to be solve
  6 KB (828 words) - 16:26, 20 February 2018
• Ultra Low Power Conversion Circuit For Batteryless Applications
  ...the expensive and obtrusive storage element. One of the biggest challenges in batteryless system design is the cold start phase, where the harvesting cir ...10 uW input power range, they are unable to operate in the nanowatt range. In this project, we want to design a DC-DC converter optimized for very low in
  3 KB (485 words) - 17:46, 10 August 2016
• Gomeza old project5
  ...ave several prototypes of batteryless sensor nodes which we want to deploy in a wide area network. * Integrating a LoRa radio in a batteryless sensor node
  3 KB (360 words) - 18:25, 28 January 2017
• 3D Ultrasound Bubble Tracking
  ...Ultrafast Ultrasound Localization Microscopy (uULM) [http://fultrasound.eu/in-vivo-super-resolution-vascular-imaging link]. This semester/master thesis focuses on the ultrafast tracking of bubbles in 3D.
  2 KB (253 words) - 20:52, 12 November 2020
• Towards The Integration of E-skin into Prosthetic Devices
  ...n) and energy harvesting during the project. The project will be supervise in collaboration with Cosmic Lab, University of Genova (prof. Maurizio Valle / ...lations), measuring power-consumption, and assessing detection performance in lab. conditions
  4 KB (631 words) - 11:39, 21 July 2017
• A Wireless Sensor Network for a Smart Building Monitor and Control
  ...ghting control can be made based on the light intensity and human presence in the monitored area sensed by light sensors and motion sensors. This approac ...e students. Measurements of the system will be performed from the students in order to evaluate power consumption reduction, reliability, functionality a
  4 KB (571 words) - 21:42, 30 July 2018
• A Wireless Sensor Network for HPC monitoring
  The rapid progress of wireless communications and embedded technologies has made wireless sens ...e students. Measurements of the system will be performed from the students in order to evaluate power consumption reduction, reliability, functionality a
  5 KB (617 words) - 16:22, 27 February 2018
• Mauro Salomon
  == Projects in Progress== category = In progress
  637 bytes (60 words) - 10:47, 5 April 2022
• Charging System for Implantable Electronics
  such an extent that its size is small enough to be implantable in rodents for charge the implant's battery while the animal is in its cage from an IR-LED
  3 KB (366 words) - 13:05, 27 April 2018
• Libria
  == Projects in Progress== category = In progress
  646 bytes (68 words) - 09:35, 26 August 2016
• Learning Image Compression with Convolutional Networks
  ...a ConvNet for a different encoding has been done several times before, but in order to optimize for best compression we need to quantize intermediate res In this project you learn the basics of ConvNets, develop such a quantization
  3 KB (362 words) - 16:25, 30 October 2020
• Bringing XNOR-nets (ConvNets) to Silicon
  ...of recognizing and classifying objects in a scene. Many popular algorithms in this area require the evaluations of multiple layers of filter banks. Almos ...it/pixel instead of ~12bit/pixel like before. The current state-of-the-art in this direction are XNOR-nets, but we want to understand them better and use
  10 KB (1,357 words) - 16:25, 30 October 2020
• Signal-Processing and Data-Compression on Beaglebone Black used as embedded HPC-performance-monitoring device
  ...t run-time. Aiming at bridging this gap, we designed and developed at IIS, in collaboration with some Commercial Partners, a scalable and highly accurate [[Category:In progress]]
  3 KB (351 words) - 16:19, 27 February 2018
• Linux Driver for built-in ADC using DMA and Programmable Real-Time Unit (PRU) support on Beaglebone Black used as embedded HPC-performance-monitoring device
  ...t run-time. Aiming at bridging this gap, we designed and developed at IIS, in collaboration with some Commercial Partners, a scalable and highly accurate ...t''' → Implementation and testing of a Linux Device Driver for the built-in Beaglebone Black ADC, using DMA support for the data-copy from the ADC HW-F
  3 KB (394 words) - 16:19, 27 February 2018
• Control an external ADC using Programmable Real-Time Unit (PRU) Subsystem on Beaglebone Black used as embedded HPC-performance-monitoring device
  ...t run-time. Aiming at bridging this gap, we designed and developed at IIS, in collaboration with some Commercial Partners, a scalable and highly accurate ...te a high-speed high-resolution ADC, which will be controlled by the built-in Programmable Real-Time Unit ([http://beagleboard.org/pru PRU]) of the Beagl
  3 KB (440 words) - 16:15, 1 September 2017
• Open Power-On Chip Controller Study and Integration
  In recent years, energy-efficiency is becoming a key challenge in the High Performance Computing (HPC) domain. Until today Intel-based comput ...aracterizing its behavioral (B) and implementing an extension of the built-in power management policy (C) which links run-time architectural information,
  3 KB (462 words) - 15:57, 9 September 2016
• Linux Driver for fine-grain and low overhead access to on-chip performance counters
  In recent years, energy-efficiency is becoming a key challenge in the High Performance Computing (HPC) domain. Indeed, while the demand for m ...experience with Linux Kernel Programming, IIO Linux Subsystem (widely used in Linux-Based SoCs for handling ADCs) and architectural performance counters.
  3 KB (417 words) - 15:55, 9 September 2016
• Ultra Low-Power Oscillator
  ...research results and to achieve a comparable efficiency as the best design in the figure. ===Status: In Progress ===
  2 KB (368 words) - 18:58, 19 December 2016
• High performance continous-time Delta-Sigma ADC for biomedical applications
  ...us-time converter for up to 10kHz bandwidth with 80dB SNR will be designed in 130nm CMOS. It will be possible to learn the whole the design cycle includi ===Status: In Progress ===
  3 KB (375 words) - 17:46, 2 May 2017
• High performance continuous-time Delta-Sigma ADC for magnetic resonance imaging
  ...ll be investigated first at behavioral level, followed by a circuit design in 130nm CMOS. It will be possible to learn the whole the design cycle includi ===Status: In Progress ===
  3 KB (358 words) - 11:40, 20 August 2021
• PVT Dynamic Adaptation in PULPv3
  ...controller algorithm is then needed to always configure the PULP processor in the most energy efficient point. The goal of this project is to compensate the process variation in the PULP v3 SoCs by (1) characterize and correlate the PVT sensors respons
  3 KB (348 words) - 15:31, 13 September 2016
• Design of low-offset dynamic comparators
  ...ated comparators with similar delay time (determined by the clock period). In this thesis different topologies will be compared to each other for resolut ===Status: In Progress ===
  3 KB (362 words) - 17:35, 21 December 2017
• Radio Signal Direction Detection For Smart Glasses For Augmented Reality Applications
  consists in applying electronic warfare concepts to estimate the conducted in collaboration with said company. Information on the
  4 KB (609 words) - 11:38, 21 July 2017
• Desing and Implementation Of Long Lasting Key Finder With Bleetooth Low Energy
  ...o life several months without change the battery. THe project will be done in collaboration with Keyfinder.ch : Interest in Computer Architectures at system level
  4 KB (502 words) - 11:38, 21 July 2017
• High Power Efficient Digitally Controlled Oscillator Design for Cellular IOT
  ...t imposed by cellular applications have been a key driver for PLL research in recent years. As the age of cellular internet of things is coming, motivati ===Status: In Progress ===
  3 KB (428 words) - 11:45, 20 August 2021
• High Performance Digitally-Assisted Time Domain ADC Design for DPLL used in Cellular IOT
  ...project is to analyze and build a time domain ADC innovatively so that the in-band jitter contribution of the DPLL could be lower than 500fs while consum ===Status: In Progress ===
  3 KB (453 words) - 11:45, 20 August 2021
• Design of Charge-Pump PLL in 22nm for 5G communication applications
  ...ch means the high purity frequency carriers are required to be synthesized in the range from 15 GHz to even 60 GHz. ...n in the figure above, there are quite many smart architectures introduced in recent years, such as injection-locking (ILPLL) and subsampling (SSPLL). Al
  4 KB (514 words) - 15:51, 20 August 2021
• Nanoscale Hybrid III-V Plasmonic Laser for Low-Power Photonic ICs
  ...quantum-transport based hybrid plasmonic laser simulator by extending our in-house quantum-transport solver with electron-photon coupling. The functiona ...by using plasmonics. By coupling photons to collective motion of electrons in metals, surface plasmon polaritons (SPPs) are formed at a metal/dielectric
  2 KB (323 words) - 17:09, 16 September 2021
• Sensor Fusion for Rockfall Sensor Node
  ...complete reconstruction of the rock trajectories. Depending on the project progress, novel approaches introducing additional sources of information can be eval
  2 KB (352 words) - 11:51, 21 August 2018
• Interfacing PULP with a Brain-Inspired Ultra-Low Power Spiking Cochlea
  ...the past two years. PULP is intended to be used for near-sensor computing in smart sensors, particularly on sensors that have a high need for extremely ...icial cochlea strives to replicate this functionality in a silicon sensor. In nature, the spiking representation conveys enough information for us to rec
  9 KB (1,427 words) - 18:36, 5 September 2019
• Towards Online Training of CNNs: Hebbian-Based Deep Learning
  ...s possible to greatly reduce the amount of data that needs to be collected in a ULP sensor node and sent to a higher-level computing device (e.g. a smart 2. implement Adaptive Hebbian Learning (AHL) as proposed in Wadhwa and Madhow [Wadhwa16] within the framework, using classification of
  6 KB (909 words) - 19:50, 30 May 2017
• Deep Learning Projects
  ...gradient descent) is linear in the data set size, making it more appealing in big data contexts than, for instance, support vector machines (SVMs). DNNs ...the pressure of DNNs on the underlying computing infrastructure, research in computational deep learning has focussed on two families of optimizations:
  18 KB (2,473 words) - 19:29, 19 February 2024
• Deep-Learning Based Phoneme Recognition from a Ultra-Low Power Spiking Cochlea
  ...s possible to greatly reduce the amount of data that needs to be collected in a ULP sensor node and sent to a higher-level computing device (e.g. a smart ...icial cochlea strives to replicate this functionality in a silicon sensor. In nature, the spiking representation conveys enough information for us to rec
  6 KB (920 words) - 16:33, 3 October 2019
• Single-Bit-Synapse Spiking Neural System-on-Chip
  Current interest in brain-inspired and neuromorphic computer architectures is enormous, due to ...starting point for the development of a novel spiking-based architecture, in this project we would like to develop a concrete proof of concept low power
  7 KB (1,000 words) - 12:22, 13 January 2017
• Tiny CNNs for Ultra-Efficient Object Detection on PULP
  ...s possible to greatly reduce the amount of data that needs to be collected in a ULP sensor node and sent to a higher-level computing device (e.g. a smart ...e-of-the-art. Relatively small CNNs with object detection accuracy results in the order of the best models available have recently been proposed [Iandola
  5 KB (794 words) - 13:19, 13 January 2017
• PULP-Shield for Autonomous UAV
  ...s the inspection of industrial facilities or cultivated fields, assistance in natural disaster or hazardous areas, etc. ...no-scale, featuring only few centimeters in diameter and few tens of grams in weight.
  6 KB (875 words) - 11:06, 23 February 2018
• Convolution Neural Networks on our Ultra-Low Power Mult-Core Plattform PULP
  Neural Nets are achieving record-breaking results in all common machine learning tasks and reached high attention of the machine ...own to be reduced by about 10% or less. (75% instead of 85% Top-1 accuracy in the sound recognition CNN.)
  6 KB (823 words) - 08:36, 20 January 2021
• VLSI Implementation Polar Decoder using High Level Synthesis
  ...nnels. This is why Polar codes have been one of the main focus of research in the communication’s society. The recent decision by the 3GPP standardizat ...architectures can be quantitatively evaluated based on the generated RTL. In order to improve the quality of results, manually optimized RTL code or eve
  3 KB (392 words) - 14:17, 5 April 2022
• FPGA-based Testbed Implementation of an Extended-Coverage Point-to-Point Communication Link for the Internet of Things
  ...all these use cases makes new communication protocols inevitable resulting in today’s IoT standardization efforts including cellular IoT (Extended-Cove ...the work throughout the project requires embedded C coding, with some work in HDL being required eventually.
  3 KB (462 words) - 13:54, 13 November 2020
• Energy-Efficient Brain-Inspired Hyperdimensional Computing
  ...most failure mechanisms and noise. There have been successful applications in variety of tasks such as: language recognition, text classification, biosig In this project, your goal would be to develop an RTL implementation of HD com
  4 KB (467 words) - 13:38, 10 November 2020
• Autoencoder Accelerator for On-Chip Semi-Supervised Learning
  ...which can be exploited by an application-specific integrated circuit ASIC, in contrast to CPUs or even GPUs. In this thesis, the students will develop an optimized Deconvolution Accelerat
  6 KB (842 words) - 08:37, 20 January 2021
• Hardware Accelerators for Lossless Quantized Deep Neural Networks
  ...level semantically rich information out of raw data is deep learning, and in particular deep convolutional neural networks (CNNs). The task of inference ...tand-alone ASICs for aggressively quantized CNNs (''YodaNN'' [Andri2017]), in the Ergo project we want to design a PULP-based entire computation cluster
  6 KB (949 words) - 13:41, 10 November 2020
• Low-Energy Cluster-Coupled Vector Coprocessor for Special-Purpose PULP Acceleration
  ...past with our platform, with the additional advantage of more flexibility in the target application. ...ith the shared memory of the PULP clusters. Techniques and ideas developed in the context of PULP HW accelerators [Conti2017][Azarkhish2017] can be used
  6 KB (916 words) - 15:50, 7 December 2018
• Embedded Audio Source Localization Exploiting Coincidence Detection in Asynchronous Spike Streams
  ...ip asynchronously outputs a stream of address-events representing activity in different audio frequency ranges. ...difference (ITD); in other words, the difference in the azimuth direction in the arrival timing of sound waves, at the two ears. Similarly to what is do
  7 KB (1,025 words) - 19:52, 30 May 2017
• A computational memory unit using phase-change memory devices
  ...ces are used to perform certain computational tasks within the memory unit in a non-von Neumann manner. ...riety of application areas such as machine learning and signal processing. In IBM Research - Zurich we have shown experimental demonstrations of this con
  4 KB (546 words) - 11:33, 17 April 2020
• Deep Learning for Brain-Computer Interface
  ...akes it particularly challenging, however, is its susceptibility to errors in the recognition of human intentions. Indeed, the recent success of deep lea ===Status: In Progress ===
  3 KB (372 words) - 20:22, 1 April 2019
• Variable Bit Precision Logic for Deep Learning and Artificial Intelligence
  ...orking principles of the brain, allowed to achieve superhuman performances in many fields, redefining the state of the art for computer vision, text and ...fixed-point precision arithmetic, aligned with the standard precision used in deep learning field.
  7 KB (1,001 words) - 10:43, 26 June 2017
• Resilient Brain-Inspired Hyperdimensional Computing Architectures
  ...ting platforms, allowing to implement resilient controllers. Its tolerance in low signal-to-noise ratio (SNR) conditions and for faulty components is ach In this project, your goal would be to design and develop an end-to-end robust
  3 KB (401 words) - 19:08, 29 January 2021
• Trace Debugger for custom RISC-V Core
  ...ing up silicon quickly and makes a software developer's life a lot easier. In smaller processors like the ones developed at IIS we rely on an external de External, in-contrast to self-hosted, debugging relies on a more powerful host machine a
  5 KB (729 words) - 11:27, 11 December 2018
• Efficient Search Design for Hyperdimensional Computing
  ...tor by using a distance metric. When the dimensionality of hypervectors is in the thousands (e.g.,100,000 bits), an efficient search operation is challen ...l would be to design an efficient and general module for search operations in HD computing. You would develop RTL implementation with FPGA prototyping.
  3 KB (366 words) - 15:39, 10 November 2020
• BigPULP: Multicluster Synchronization Extensions
  ...stantial number of tape outs of various single-cluster PULP configurations in multiple technology nodes [1]. A key component allowing for high energy-eff ...formance, e.g., to use use PULP as a high-performance parallel accelerator in heterogeneous systems. To this end, we also study the seamless integration
  6 KB (805 words) - 12:17, 22 January 2018
• BigPULP: Shared Virtual Memory Multicluster Extensions
  ...stantial number of tape outs of various single-cluster PULP configurations in multiple technology nodes [1]. A key component allowing for high energy-eff ...formance, e.g., to use use PULP as a high-performance parallel accelerator in heterogeneous systems. To this end, we also study the seamless integration
  6 KB (801 words) - 15:05, 23 August 2018
• Hyper Meccano: Acceleration of Hyperdimensional Computing
  ...al component or its immediate neighbors. Other operations can be performed in a distributed fashion. ...omputational paradigm that is easily applied to various learning problems. In this project, your goal is to accelerate, optimize, and autotune execution
  3 KB (409 words) - 13:58, 9 November 2017
• Stefan Lippuner
  Stefan left the IIS in 2022. == Projects in Progress==
  532 bytes (49 words) - 10:47, 24 November 2022
• LTE IoT Network Synchronization
  ...ings. Two new variants of LTE have been standardized as part of Release 13 in 2016 for this kind of device: LTE Cat-M1 (eMTC) and NB-IoT. They both offer Network synchronization is the first step in the communication between the user equipment (UE) and the base station. It
  3 KB (440 words) - 16:32, 18 May 2018
• IoT Turbo Decoder
  ...ceived data iteratively. Several Turbo Decoders have been developed at IIS in the past ([[High_Throughput_Turbo_Decoder_Design|e.g.]]), which were mainly ...the IoT, a new variant of LTE have been standardized as part of Release 13 in 2016: LTE Cat-M1 (eMTC). This category offers only a reduced throughput of
  3 KB (427 words) - 09:37, 14 September 2018
• High Speed FPGA Trigger Logic for Particle Physics Experiments
  ...pa.phys.ethz.ch/ Physics Department of ETH Zurich]. If you are experienced in FPGA programming (VHDL) and want to spice up your knowledge with a real wor ...ssues a signal for data taking or not). The Xilinx AC701 Development Board in combination with a recently designed and build interface board (see picture
  4 KB (460 words) - 21:42, 30 January 2018
• Satellite Internet of Things
  ...d in fact the extended-coverage would enable communication with satellites in Low Earth Orbits (LEO). But, the NB-IoT standard is optimized for slowly mo ...able the identification of critical bottlenecks. These shall be eliminated in the second part of the project by algorithmic optimizations and/or changes
  3 KB (393 words) - 13:53, 13 November 2020
• Neural Networks Framwork for Embedded Plattforms
  ...like Torch or Tensorflow to evaluate and train the network and export it in a compilable form for efficient inference on the previously mentioned platf [[Category:In progress]]
  3 KB (317 words) - 14:40, 14 April 2021
• BLISS - Battery-Less Identification System for Security
  ...the significant power consumption prevent this technology to be exploited in small, wearable, battery-powered and autonomous devices. ...task, the project is split into 2 projects, which can possibly be combined in the end.
  4 KB (602 words) - 10:45, 31 January 2023
• HERO: TLB Invalidation
  ...stantial number of tape outs of various single-cluster PULP configurations in multiple technology nodes. ...formance, e.g., to use use PULP as a high-performance parallel accelerator in heterogeneous systems. To this end, we also study the seamless integration
  6 KB (796 words) - 17:19, 18 November 2019
• Shared Correlation Accelerator for an RF SoC
  ...rk synchronization rely on performing a large number of cross-correlations in real-time. Due to the large throughput requirements, large accelerators are ...cross-correlations. Using this knowledge, you will develop the accelerator in VHDL, or using High-Level Synthesis (HLS). It should be able to meet the th
  3 KB (421 words) - 09:38, 14 September 2018
• Deep Convolutional Autoencoder for iEEG Signals
  In this thesis, the students will develop a deep convolutional autoencoder to * project report (in digital form; a hard copy also welcome, but not necessary)
  5 KB (641 words) - 13:36, 9 September 2020
• Heterogeneous SoCs
  ...le:Apple_heterogeneous_integration.png|700px|thumb|center|Uniting many ICs in a single one: Heterogeneous integration has allowed (not only) Apple to get ...currently one of the main drivers for performance-per-energy advancements in various application domains.
  3 KB (421 words) - 18:41, 28 October 2020
• Event-Driven Computing
  ...orth to run expensive computations or whether there is not enough activity in the environment. This approach is called event-driven computing. ===Projects In Progress===
  2 KB (266 words) - 11:16, 5 November 2020
• Predictable Execution
  ...on the same chip as the host CPU, sharing a single DRAM. This has benefits in both programability and performance, due to the removal of the need for dat ...l-time guarantees can be provided, enabling the use of these architectures in a real-time setting.
  2 KB (286 words) - 18:48, 10 November 2020
• Aliasing-Free Wavetable Music Synthesizer
  ...digital signal processors (DSPs) or field-programmable gate arrays (FPGAs) in order to generate the wavetable synthesis oscillator signals, to the best o ...LAB with the goal of minimizing aliasing while offering great flexibility. In the second step, a VLSI architecture and ASIC will be designed. The goal is
  5 KB (621 words) - 18:09, 9 October 2022

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