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- [[File:origami-fpga-system.png|400px|thumb]] ...o finish the processing pipeline (activation, pooling), and completing the system by connecting a camera or loading a video stream and displaying the results3 KB (397 words) - 18:17, 29 August 2016
- <!--[[File:origami-fpga-system.png|400px|thumb]] --> [[Category:Hot]] [[Category:Digital]] [[Category:System Design]] [[Category:Completed]] [[Category:Semester Thesis]] [[Category:Mas2 KB (285 words) - 18:16, 29 August 2016
- [1] 3GPP. Cellular System Support for Ultra Low Complexity and Low Throughput Internet of Things. htt4 KB (582 words) - 20:00, 26 September 2017
- [[File:iPMU.png|600px|thumb|right|iPMU within a Generalized System]] ...ilable energy for the system and learn the energy consumption of different system tasks. Moreover, the iPMU should profile the available power input from the2 KB (292 words) - 11:40, 2 June 2021
- ...such as battery or supercapacitor for future use. A correctly dimensioned system will guarantee the node’s operation during periods of energy unavailabili3 KB (366 words) - 18:04, 28 January 2017
- ...rs. In our lab, we have developed a energy management unit, which allows a system designer to provide energy guarantees solely from volatile energy harvestin [[Category:System Design]]3 KB (413 words) - 15:21, 28 January 2016
- [[Category:Software]] [[Category:System]] [[Category:Completed]] [[Category:Semester Thesis]] [[Category:2016]] * Interest in computer vision and system engineering5 KB (747 words) - 18:04, 29 August 2016
- [[Category:System Design]]3 KB (426 words) - 11:41, 21 July 2017
- : VHDL/System Verilog knowledge3 KB (377 words) - 10:25, 5 November 2019
- ...ultra low power consumption are the most important requirements of such a system. For this purpose a processor which only supports the basic instructions is : VHDL/System Verilog knowledge3 KB (384 words) - 17:24, 21 August 2019
- ...wn approach to improve the overall performance of a wireless communication system. The underlying principle is to feed back soft information from the channel [[Category:System Design]]3 KB (450 words) - 11:43, 13 November 2018
- ...w evaluation platform based on the Juno ARM Development Platform [3]. This system combines a modern ARMv8 multicluster CPU with a Xilinx Virtex-7 XC7V2000T F : VHDL/System Verilog, C5 KB (711 words) - 10:27, 5 November 2019
- [[Category:System Design]]3 KB (402 words) - 15:31, 13 April 2016
- [[Category:System Design]]3 KB (418 words) - 14:01, 13 November 2020
- Most of the applications do not need an always-on system and often implement aggressive duty cycling to minimize the average power c *Control system DMA to save/restore L1 data memory2 KB (236 words) - 08:35, 20 January 2021
- ...o maintain as much as possible the general purpouse phylosofy of the whole system.2 KB (237 words) - 10:27, 5 November 2019
- [[Category:System Design]]4 KB (555 words) - 16:36, 23 May 2018
- ...tion of the FPUs and therefore reduce the overall power consumption of the system. We have already designed a FPU unit with support for FP-additions, FP-subt ...dware efficient architecture for a fused multiply-add FPU, implement it in System Verilog and plug it to the RISC-V processor.2 KB (346 words) - 10:26, 5 November 2019
- : Knowledge of a hardware design language such as (System)Verilog or VHDL. [[Category:System Design]]4 KB (522 words) - 13:38, 10 November 2020
- [[Category:System Design]]3 KB (403 words) - 20:45, 9 August 2016
- : 20% VHDL/System Verilog, FPGA Design : VHDL/System Verilog, C5 KB (712 words) - 17:57, 7 November 2017
- ...ngs of arbitrary size, independent of the page size of the Linux operating system running on the host CPU. In a student project [4], a second, set-associativ ...and give access to it to user-space applications through, e.g., an mmap() system call. Ideally, all data shared with the accelerator is placed in this secti6 KB (866 words) - 13:43, 29 November 2019
- ...al-world handset operations in the wide-band code-division multiple-access system. Large-frequency and clock errors are induced at initial search due to an i2 KB (340 words) - 10:39, 6 November 2017
- [4] Scaramuzza et al., Vision-Controlled Micro Flying Robots: From System Design to Autonomous Navigation and Mapping in GPS-Denied Environments, htt6 KB (828 words) - 16:26, 20 February 2018
- ...nd obtrusive storage element. One of the biggest challenges in batteryless system design is the cold start phase, where the harvesting circuit needs to self- Finally a full system which include the energy harvesting and a sensor (a ultra low power camera3 KB (485 words) - 17:46, 10 August 2016
- ...setup a basic ultrasound simulation for a moderate (1024) channel count 3D system based on existing scripts. Then he has to assess several tracking algorithm [[Category:System Design]]2 KB (253 words) - 20:52, 12 November 2020
- [[Category:System Design]]2 KB (320 words) - 10:56, 10 January 2017
- ...nd eventually supply it with energy harvesting from the human body. A full system will be developed that will incldue the processing part, the wireless inter [[Category:System Design]]4 KB (631 words) - 11:39, 21 July 2017
- ...sor and actuator networks (WSANs) possible. These networks are distributed system consisting of nodes with sensors, intelligence and actuator interconnected ...e power consumption reduction, reliability, functionality and optimize the system.4 KB (571 words) - 21:42, 30 July 2018
- ..., televisions, pc among others. The main goal is to achieve an intelligent system that process the data from one or more sensors to understand the context an ...classification accuracy and energy efficiency and to further optimize the system.5 KB (669 words) - 17:22, 31 January 2018
- ...s kind of communication. The project will also focus on how make the whole system self-sustaining using RF energy harvesting or other kind of energy harvesti [[Category:System Design]]4 KB (576 words) - 16:58, 28 July 2017
- ...sor and actuator networks (WSANs) possible. These networks are distributed system consisting of nodes with sensors interconnected by wireless links. We want ...e power consumption reduction, reliability, functionality and optimize the system.5 KB (617 words) - 16:22, 27 February 2018
- ...ard-FPGA and to implement the control sidechannel interface to the backend system (a PC in our case). * Design an interface/API such that the firmware can talk to the backend system (UART based)3 KB (458 words) - 20:51, 12 November 2020
- Using mixed-signal SoCs developed at IIS it is possible to integrate a system to conducting medical research. Despite low power consumption of the system the3 KB (366 words) - 13:05, 27 April 2018
- <!--[[File:origami-fpga-system.png|400px|thumb]] --> [[Category:Hot]] [[Category:Digital]] [[Category:System Design]] [[Category:Semester Thesis]] [[Category:Master Thesis]] [[Category3 KB (362 words) - 16:25, 30 October 2020
- ...nodes. Computing nodes based on ARM SoCs are facing the market, as well as system based on the IBM power architecture. To create more market opportunities IB *Good computer architecture and real-time system background.3 KB (462 words) - 15:57, 9 September 2016
- *Knowledge of the Linux Operating System architecture3 KB (417 words) - 15:55, 9 September 2016
- ...ansport this data-rate efficiently from the head to the backend processing system, we use a optical high-speed link. ...d software IPs. Using these IPs allows to build rather easily very complex system. You will be extensively working with the Xilinx Vivado Tool.3 KB (409 words) - 10:55, 10 January 2017
- ...on the power consumption of those circuits that are always on, like e.g. a system clock. So this topic has seen a lot of attention in recent years. The aim o2 KB (368 words) - 18:58, 19 December 2016
- ...nm CMOS. It will be possible to learn the whole the design cycle including system simulation and layout as a master student, for a semester thesis the work w : 20% System Simulation (Matlab/Simulink)3 KB (375 words) - 17:46, 2 May 2017
- ...nm CMOS. It will be possible to learn the whole the design cycle including system simulation and layout as a master student. : 20% System Simulation (Matlab/Simulink)3 KB (358 words) - 11:40, 20 August 2021
- ...esis]] [[Category:2016]] [[Category:Barandre]][[Category:PULP]][[Category:System Design]] ...nts the software control loop which maximizes the energy efficiency of the system dynamically tracking the PVT variations3 KB (348 words) - 15:31, 13 September 2016
- ...ors that are always on are usually slow and exhibit too much noise. When a system clock is available dynamic comparators are an attractive alternative, as th3 KB (362 words) - 17:35, 21 December 2017
- Mixed-signal system-on-chips (SoCs) often consist of various independent subsystems (e.g., diff3 KB (389 words) - 11:20, 14 September 2016
- The student will design and implement an ultra low power system testing the performances of the whole system by using a commercial RF4 KB (609 words) - 11:38, 21 July 2017
- ...main goal of the design is to optimize the power consumption to allow the system to life several months without change the battery. THe project will be done : Interest in Computer Architectures at system level4 KB (502 words) - 11:38, 21 July 2017
- system.6 KB (900 words) - 16:58, 7 May 2018
- As the key for wireless transceiver system, Phase-locked loop (PLL) is a general solution for frequency synthesize. In4 KB (514 words) - 15:51, 20 August 2021
- #REDIRECT [[System Analysis and VLSI Design of LTE NB-IoT Baseband Processing]]79 bytes (11 words) - 09:49, 19 October 2016
- #REDIRECT [[System Analysis and VLSI Design of NB-IoT Baseband Processing]]75 bytes (10 words) - 09:49, 19 October 2016
- [[Category:System Design]]2 KB (259 words) - 11:34, 10 November 2017
- [[Category:System Software]]2 KB (352 words) - 11:51, 21 August 2018
- ...(IIS) we have been working on a Parallel Ultra-Low Power Processor (PULP) System for the past two years. PULP is intended to be used for near-sensor computi ...e with basic engineering tools (web search, basic usage of Linux operating system, compilers…) and of work independence9 KB (1,427 words) - 18:36, 5 September 2019
- ...ast few years along the entire technological stack, from HW (e.g. the PULP system) to SW running on microcontrollers – in many cases using convolutional ne6 KB (909 words) - 19:50, 30 May 2017
- #REDIRECT [[WCDMA/HSPA+ Synchronization System Design, Implementation, and Testing]]84 bytes (9 words) - 15:33, 1 December 2016
- ...in which the signal is digitized directly in the probe and sent to the US system through an optical fiber. This digitization enables a higher flexibility fo [[Category:System Design]]4 KB (521 words) - 10:37, 26 October 2021
- [[File:Ultralight.jpg|thumb|400px|Current Prototype System]] * Programming of software functions: Microcontroller Programming / Processing system programming (C/C++/CUDA)2 KB (254 words) - 14:14, 31 October 2020
- ...head. The beamformer is the core processing unit in any ultrasound imaging system as it produces the image from the raw sensor data. Similar to other handhel ...figures the beamformer based on real-time temperature sensor data from the system.3 KB (374 words) - 20:50, 12 November 2020
- ...rly defined algorithmic problem and actually test the result in a complete system with real world data.2 KB (295 words) - 11:27, 6 November 2017
- ...ast few years along the entire technological stack, from HW (e.g. the PULP system) to SW running on microcontrollers – in many cases using convolutional ne6 KB (920 words) - 16:33, 3 October 2019
- ...his project we would like to develop a concrete proof of concept low power System-on-Chip where (small) practical applications such as Spiking Convolutional ...connected. With regard to this, a higher-level synaptic array for the full System-on-Chip must be designed, taking into account even more strict area constra7 KB (1,000 words) - 12:22, 13 January 2017
- ...ast few years along the entire technological stack, from HW (e.g. the PULP system) to SW running on microcontrollers – in many cases using convolutional ne5 KB (794 words) - 13:19, 13 January 2017
- * Familiarity with embedded system programming in C. [3] Altium Design System http://www.altium.com/6 KB (875 words) - 11:06, 23 February 2018
- ...classification accuracy and energy efficiency and to further optimize the system. [[Category:System Design]]5 KB (703 words) - 17:21, 31 January 2018
- [[Category:System Design]]3 KB (392 words) - 14:17, 5 April 2022
- Within this project, you will built such a system. It should be able to quickly and robustly scan the labels and provide the ...care, image processing and interface design. A successful implement of the system will improve patient care by reducing the workload on the intensive care st2 KB (315 words) - 13:00, 22 February 2017
- [[Category:System Design]]3 KB (462 words) - 13:54, 13 November 2020
- ...L implementation of HD computing for an EMG-based hand gesture recognition system with fast learning using much lower power than ever before. [[Category:System Design]]4 KB (467 words) - 13:38, 10 November 2020
- * Knowledge of a hardware design language: e.g. (System)Verilog or VHDL6 KB (842 words) - 08:37, 20 January 2021
- ...ry purpose of this project is to contribute to the ''Ergo'' deep inference System-on-Chip by designing HW/SW techniques for the acceleration of aggressively ...f hardware design and computer architecture - having followed the Advances System-on-Chip Design course is recommended6 KB (949 words) - 13:41, 10 November 2020
- ...f hardware design and computer architecture - having followed the Advanced System-on-Chip Design course is recommended * [Conti2017] F. Conti et al., An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics [https://arxi6 KB (916 words) - 15:50, 7 December 2018
- The prototype system on which the source localization application will be implemented is constit ...of sound waves, at the two ears. Similarly to what is done by our auditory system to detect the azimuthal direction of a sound, by looking at the time differ7 KB (1,025 words) - 19:52, 30 May 2017
- [[Category:System Design]]4 KB (546 words) - 11:33, 17 April 2020
- [[Category:System Design]]3 KB (372 words) - 20:22, 1 April 2019
- ...f hardware design and computer architecture - having followed the Advances System-on-Chip Design course is recommended * [Conti2017] F. Conti et al., An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics, [https://arx7 KB (1,001 words) - 10:43, 26 June 2017
- [[Category:System Design]]3 KB (401 words) - 19:08, 29 January 2021
- ...e HDL (hardware description language) of your choice (for example VHDL or (System)-Verilog) as thought in VLSI I and II ...lel Computing Systems for Data Analytics class (formerly known as Advanced System on a Chip)5 KB (729 words) - 11:27, 11 December 2018
- [[File:Hyperdimensional-Solar-System.jpg|thumb]] [[Category:System Design]]3 KB (366 words) - 15:39, 10 November 2020
- ...he existing LightProbe prototype with a Wireless LAN module to provide the system with a low-rate (Mbit/s) interface to connect directly with a mobile phone ...ples are provided) and write the required scripts/program on the receiving system (can be a laptop) to capture the sent data.2 KB (324 words) - 16:59, 16 September 2022
- * VHDL or (System)-Verilog knowledge, VLSI I & II4 KB (603 words) - 09:37, 10 July 2018
- both dramatically simplifying the programmability of such a heterogeneous system. ...aluation platform [5] based on the Juno ARM Development Platform [6]. This system combines a modern ARMv8 multicluster CPU with a Xilinx Virtex-7 XC7V2000T F6 KB (805 words) - 12:17, 22 January 2018
- both dramatically simplifying the programmability of such a heterogeneous system. ...aluation platform [5] based on the Juno ARM Development Platform [6]. This system combines a modern ARMv8 multicluster CPU with a Xilinx Virtex-7 XC7V2000T F6 KB (801 words) - 15:05, 23 August 2018
- initiatives such as the Heterogeneous System Architecture foundation (HSA) are access to system memory from both sides, eliminating the need for explicit6 KB (865 words) - 12:16, 17 November 2017
- ...detectors) to reduce the power consumption but also use energy harvesting system such as microbial fuel cell. The communication plays also an important role ...ment of novel zero-power sensors that act as a trigger for the rest of the system when important event is detected and consume zero-power between two detecti5 KB (745 words) - 17:21, 31 January 2018
- [[Category:System Design]]3 KB (409 words) - 13:58, 9 November 2017
- [[Category:System Design]] [[Category:System on Chips for IoTs]]4 KB (460 words) - 21:42, 30 January 2018
- ...iver, digital baseband processing, and an application processor. Such a RF System-on-Chip (RF-SoC) is mandatory to achieve minimal manufacturing costs.3 KB (344 words) - 01:45, 10 February 2021
- ...nology to cellular connectivity by covering dead spots or as a stand-alone system. NB-IoT itself is seen as a possible technology for satellite IoT (sIoT) an ...upport satellite communication channels. A thorough simulative analysis of system performance will enable the identification of critical bottlenecks. These s3 KB (393 words) - 13:53, 13 November 2020
- [[Category:System Design]] [[Category:System Design]]3 KB (317 words) - 14:40, 14 April 2021
- ...bedded image processing. The ambitious goal is to build a self-sustainable system that allows simple image processing to be implemented on-board the device. ...dy the required components for building a miniature ultra-low power camera system and develop a demonstration platform based on our ULP image sensor chip (de4 KB (602 words) - 10:45, 31 January 2023
- both dramatically simplifying the programmability of such a heterogeneous system. ...al of this project is to implement TLB invalidations for our heterogeneous system.6 KB (796 words) - 17:19, 18 November 2019
- ...is a great cellular IoT research opportunity and gives deep insights into system engineering.2 KB (269 words) - 13:15, 31 October 2019
- ...in including RF front-end, dedicated digital baseband hardware, and a CPU system. But, expected area and therefore cost as well as power consumption show ro1 KB (217 words) - 11:01, 18 March 2019
- ...detection and location of such seizures. When aiming a low power implanted system the large amount of data has to be efficiently reduced. iEEG signals are sp5 KB (641 words) - 13:36, 9 September 2020
- ...exploit their theoretical potential is challenging due to the high overall system complexity. ...our chance to explore and work on (almost) any layer of a running computer system and contribute to energy-efficient next-generation computing platforms!3 KB (421 words) - 18:41, 28 October 2020
- ...be deployed on COTS hardware that limit the memory interference within the system, such that real-time guarantees can be provided, enabling the use of these2 KB (286 words) - 18:48, 10 November 2020
- ...ize, and will thus constitute an increasingly larger fraction of the total system power consumption. * '''2020''' - V. Niculescu et Al., "An Energy-efficient Localization System for Imprecisely Positioned Sensor Nodes with Flying UAVs", ''2020 IEEE 18th14 KB (2,077 words) - 15:02, 13 June 2022
- [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]5 KB (621 words) - 18:09, 9 October 2022
- [[Category:System on Chips for IoTs]] [[Category:Biomedical System on Chips]]5 KB (549 words) - 12:35, 28 November 2022
- At IIS, we are exploring the next generation of medical ultrasound system. Our Flagship projects are: ...rable solutions as well as alternatives to the traditional bulky and rigid system designs.6 KB (797 words) - 16:16, 23 February 2024